From patchwork Fri Oct 26 16:42:42 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jesse Barnes X-Patchwork-Id: 1652771 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-process-083081@patchwork1.kernel.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by patchwork1.kernel.org (Postfix) with ESMTP id 0ABC340135 for ; Fri, 26 Oct 2012 16:42:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 01C349EB43 for ; Fri, 26 Oct 2012 09:42:58 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from oproxy6-pub.bluehost.com (oproxy6-pub.bluehost.com [67.222.54.6]) by gabe.freedesktop.org (Postfix) with SMTP id E52D09E78D for ; Fri, 26 Oct 2012 09:42:44 -0700 (PDT) Received: (qmail 12529 invoked by uid 0); 26 Oct 2012 16:42:44 -0000 Received: from unknown (HELO box514.bluehost.com) (74.220.219.114) by cpoproxy3.bluehost.com with SMTP; 26 Oct 2012 16:42:44 -0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=virtuousgeek.org; s=default; h=Content-Transfer-Encoding:Content-Type:Mime-Version:References:In-Reply-To:Message-ID:Subject:Cc:To:From:Date; bh=05mhEJaHrgfIb5yvDVB6aM+E9EaWwLjYz3EYCTU+ss8=; b=npSBuzn/vjnU++YjLyDhxlaqdKCdqJ0DQXF+LLwtKL9Q43Lt2RjteeN4W/OHZNdCczFI5Rq0yqV6bRIQD/qCFEH9xsrqjZY2g8KGUqZH9jtN6xfohM2kkRn1jb8bFNxs; Received: from [67.161.37.189] (port=47939 helo=jbarnes-desktop) by box514.bluehost.com with esmtpsa (TLSv1:AES128-SHA:128) (Exim 4.76) (envelope-from ) id 1TRmza-0004vs-IW; Fri, 26 Oct 2012 10:42:42 -0600 Date: Fri, 26 Oct 2012 09:42:42 -0700 From: Jesse Barnes To: Chris Wilson Message-ID: <20121026094242.0c74d329@jbarnes-desktop> In-Reply-To: References: <1351192548-2992-1-git-send-email-jbarnes@virtuousgeek.org> <1351192548-2992-6-git-send-email-jbarnes@virtuousgeek.org> X-Mailer: Claws Mail 3.8.0 (GTK+ 2.24.10; x86_64-pc-linux-gnu) Mime-Version: 1.0 X-Identified-User: {10642:box514.bluehost.com:virtuous:virtuousgeek.org} {sentby:smtp auth 67.161.37.189 authed with jbarnes@virtuousgeek.org} Cc: intel-gfx@lists.freedesktop.org Subject: Re: [Intel-gfx] [PATCH 6/8] drm/i915: TLB invalidation with MI_FLUSH_DW requires a post-sync op X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+patchwork-intel-gfx=patchwork.kernel.org@lists.freedesktop.org On Fri, 26 Oct 2012 12:13:39 +0100 Chris Wilson wrote: > On Thu, 25 Oct 2012 12:15:46 -0700, Jesse Barnes wrote: > > So store into the scratch space of the HWS to make sure the invalidate > > occurs. > > > > v2: use GTT address space for store, clean up #defines (Chris) > > > > Signed-off-by: Jesse Barnes > > --- > > @@ -1460,10 +1467,17 @@ static int blt_ring_flush(struct intel_ring_buffer *ring, > > return ret; > > > > cmd = MI_FLUSH_DW; > > + /* > > + * Bspec vol 1c.3 - blitter engine command streamer: > > + * "If ENABLED, all TLBs will be invalidated once the flush > > + * operation is complete. This bit is only valid when the > > + * Post-Sync Operation field is a value of 1h or 3h." > > + */ > > if (invalidate & I915_GEM_DOMAIN_RENDER) > > - cmd |= MI_INVALIDATE_TLB; > > + cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | > > + MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_OP_STOREDW; > > intel_ring_emit(ring, cmd); > > - intel_ring_emit(ring, 0); > > + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_INDEX | MI_FLUSH_DW_USE_GTT); > > s/SCRATCH_INDEX/SCRATCH_ADDR/ > -Chris > Reviewed-by: Chris Wilson diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index f29401b..ea97430 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -242,8 +242,12 @@ */ #define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1) #define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */ -#define MI_INVALIDATE_TLB (1<<18) -#define MI_INVALIDATE_BSD (1<<7) +#define MI_FLUSH_DW_STORE_INDEX (1<<21) +#define MI_INVALIDATE_TLB (1<<18) +#define MI_FLUSH_DW_OP_STOREDW (1<<14) +#define MI_INVALIDATE_BSD (1<<7) +#define MI_FLUSH_DW_USE_GTT (1<<2) +#define MI_FLUSH_DW_USE_PPGTT (0<<2) #define MI_BATCH_BUFFER MI_INSTR(0x30, 1) #define MI_BATCH_NON_SECURE (1) /* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 785df4f..55abda5 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1395,10 +1395,17 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring, return ret; cmd = MI_FLUSH_DW; + /* + * Bspec vol 1c.5 - video engine command streamer: + * "If ENABLED, all TLBs will be invalidated once the flush + * operation is complete. This bit is only valid when the + * Post-Sync Operation field is a value of 1h or 3h." + */ if (invalidate & I915_GEM_GPU_DOMAINS) - cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; + cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD | + MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; intel_ring_emit(ring, cmd); - intel_ring_emit(ring, 0); + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); intel_ring_emit(ring, 0); intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); @@ -1460,10 +1467,17 @@ static int blt_ring_flush(struct intel_ring_buffer *ring, return ret; cmd = MI_FLUSH_DW; + /* + * Bspec vol 1c.3 - blitter engine command streamer: + * "If ENABLED, all TLBs will be invalidated once the flush + * operation is complete. This bit is only valid when the + * Post-Sync Operation field is a value of 1h or 3h." + */ if (invalidate & I915_GEM_DOMAIN_RENDER) - cmd |= MI_INVALIDATE_TLB; + cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX | + MI_FLUSH_DW_OP_STOREDW | MI_FLUSH_DW_OP_STOREDW; intel_ring_emit(ring, cmd); - intel_ring_emit(ring, 0); + intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT); intel_ring_emit(ring, 0); intel_ring_emit(ring, MI_NOOP); intel_ring_advance(ring); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 3745d1d..5af65b8 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -183,6 +183,8 @@ intel_read_status_page(struct intel_ring_buffer *ring, * The area from dword 0x20 to 0x3ff is available for driver usage. */ #define I915_GEM_HWS_INDEX 0x20 +#define I915_GEM_HWS_SCRATCH_INDEX 0x30 +#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);