From patchwork Wed Mar 5 06:31:58 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 3770821 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 053CABF13A for ; Wed, 5 Mar 2014 06:32:10 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id F220920225 for ; Wed, 5 Mar 2014 06:32:08 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id B076120222 for ; Wed, 5 Mar 2014 06:32:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 80AAAFA240; Tue, 4 Mar 2014 22:32:05 -0800 (PST) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-pa0-f53.google.com (mail-pa0-f53.google.com [209.85.220.53]) by gabe.freedesktop.org (Postfix) with ESMTP id 0A7DDFA240 for ; Tue, 4 Mar 2014 22:32:03 -0800 (PST) Received: by mail-pa0-f53.google.com with SMTP id ld10so656798pab.40 for ; Tue, 04 Mar 2014 22:32:02 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-type:content-disposition:in-reply-to :user-agent; bh=CgBJp++QeCfhkVPuvuuO/1YHaRnOWcmFhBscpz1rOiI=; b=SmdGHyWzvKl/dS8Pn87HH7mqP88Pnm1Sy8nAqyhs4NDNgkDoBzIrHiYGqHcqeDIY93 oi+Yn/t6GS5SUmHGYFm/jjed5acNLukExBo5qs88LR57l1tcNhrVOq1ujmFz72R9mx/9 LdQgBm/ukKMlNnxxHRi7rVJyd4i7bf383R0qxIfGcnBW+wugfyLHYIN26jpaN4TCKG0s uWnCDx2dECYuUXFIEPb+BQ+sHBaO5x9t1hXrOJFIb5T2TEcMgbT/QQsShypHP7yUzRO1 Voyi62SWyaelCyD7lPckRgOwPHbDOF5i0tutF+7xc5hCI9Kc30dpknv9SJv0iLdikegi gSkA== X-Gm-Message-State: ALoCoQnE4ZtRFaCpNsEzNaMWBb2gIBoMYTVijI/97uXrx3H7RJT2yABmjHj/lSKjzyehvbTCo2W+ X-Received: by 10.66.246.229 with SMTP id xz5mr4577923pac.119.1394001122787; Tue, 04 Mar 2014 22:32:02 -0800 (PST) Received: from intel.com (c-24-21-100-90.hsd1.or.comcast.net. [24.21.100.90]) by mx.google.com with ESMTPSA id f5sm8676693pat.11.2014.03.04.22.32.00 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 04 Mar 2014 22:32:00 -0800 (PST) Date: Tue, 4 Mar 2014 22:31:58 -0800 From: Ben Widawsky To: "Kumar, Kiran S" Message-ID: <20140305063158.GA21767@intel.com> References: <874n7scv6a.fsf@intel.com> <1383633905-18166-1-git-send-email-benjamin.widawsky@intel.com> <8506592BE1D7B64680288B9B8A90F319017D6B97@BGSMSX101.gar.corp.intel.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <8506592BE1D7B64680288B9B8A90F319017D6B97@BGSMSX101.gar.corp.intel.com> User-Agent: Mutt/1.5.22 (2013-10-16) Cc: "Nikula, Jani" , Intel GFX , Ben Widawsky Subject: Re: [Intel-gfx] [PATCH 50/62] [v5] drm/i915/bdw: Support eDP PSR X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This is a bug. Someone needs to send me back to C-programmer school. Bits 26:25 are reserved in the spec. Furthermore, there shouldn't be a functional difference since link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25). So you found the bug, but I think the solution is actually: On Tue, Mar 04, 2014 at 09:31:28AM +0000, Kumar, Kiran S wrote: > Hi Ben, > > Can you please let me know the reason for explicit about not setting min link entry time for BDW. During my PSR testing on BDW, I found perf counter not getting increment and SRD control is setting to 0x0 with the following check: > IS_BROADWELL(dev) ? 0 : link_entry_time > > When I remove and used only "link_entry_time" without check for BDW, PSR worked fine. (perf counter started incrementing) > > Thanks > Kiran > > -----Original Message----- > From: intel-gfx-bounces@lists.freedesktop.org [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf Of Ben Widawsky > Sent: Tuesday, November 05, 2013 12:15 PM > To: Intel GFX > Cc: Nikula, Jani; Ben Widawsky; Widawsky, Benjamin > Subject: [Intel-gfx] [PATCH 50/62] [v5] drm/i915/bdw: Support eDP PSR > > Broadwell PSR support is a superset of Haswell. With this simple register base calculation, everything that worked on HSW for eDP PSR should work on BDW. > > Note that Broadwell provides additional PSR support. This is not addressed at this time. > > v2: Make the HAS_PSR include BDW > > v3: Use the correct offset (I had incorrectly used one from my faulty > brain) (Art!) > > v4: It helps if you git add > > v5: Be explicit about not setting min link entry time for BDW. This should be no functional change over v4 (Jani) > > Reviewed-by: Art Runyan > Reviewed-by: Jani Nikula > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_drv.h | 2 +- > drivers/gpu/drm/i915/i915_reg.h | 4 ++-- drivers/gpu/drm/i915/intel_dp.c | 3 ++- > 3 files changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f222eb4..dc79a0f 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1808,7 +1808,7 @@ struct drm_i915_file_private { > #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) > #define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_GEN8(dev)) > #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) > -#define HAS_PSR(dev) (IS_HASWELL(dev)) > +#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) > > #define INTEL_PCH_DEVICE_ID_MASK 0xff00 > #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ba1fe7e..3761c80 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1959,8 +1959,8 @@ > #define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B) #define VSYNCSHIFT(trans) _TRANSCODER(trans, _VSYNCSHIFT_A, _VSYNCSHIFT_B) > > -/* HSW eDP PSR registers */ > -#define EDP_PSR_BASE(dev) 0x64800 > +/* HSW+ eDP PSR registers */ > +#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800) > #define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0) > #define EDP_PSR_ENABLE (1<<31) > #define EDP_PSR_LINK_DISABLE (0<<27) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7725f81..6e4246f 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1603,6 +1603,7 @@ static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) > uint32_t max_sleep_time = 0x1f; > uint32_t idle_frames = 1; > uint32_t val = 0x0; > + const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES; > > if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) { > val |= EDP_PSR_LINK_STANDBY; > @@ -1613,7 +1614,7 @@ static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) > val |= EDP_PSR_LINK_DISABLE; > > I915_WRITE(EDP_PSR_CTL(dev), val | > - EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES | > + IS_BROADWELL(dev) ? 0 : link_entry_time | > max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | > idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | > EDP_PSR_ENABLE); > -- > 1.8.4.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index c512d78..2c0ceb4 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1723,7 +1723,7 @@ static void intel_edp_psr_enable_source(struct intel_dp *intel_dp) val |= EDP_PSR_LINK_DISABLE; I915_WRITE(EDP_PSR_CTL(dev), val | - IS_BROADWELL(dev) ? 0 : link_entry_time | + (IS_BROADWELL(dev) ? 0 : link_entry_time) | max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT | idle_frames << EDP_PSR_IDLE_FRAME_SHIFT | EDP_PSR_ENABLE);