From patchwork Thu Aug 20 04:00:20 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zhiyuan Lv X-Patchwork-Id: 7040641 Return-Path: X-Original-To: patchwork-intel-gfx@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 35F8E9F344 for ; Thu, 20 Aug 2015 04:13:13 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 2FF0C20390 for ; Thu, 20 Aug 2015 04:13:12 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 9E0172038A for ; Thu, 20 Aug 2015 04:13:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7E1886E06F; Wed, 19 Aug 2015 21:13:09 -0700 (PDT) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTP id 8BB816E06F for ; Wed, 19 Aug 2015 21:13:08 -0700 (PDT) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga103.jf.intel.com with ESMTP; 19 Aug 2015 21:13:07 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.15,713,1432623600"; d="scan'208";a="628808915" Received: from zlv-hp-dev.bj.intel.com (HELO zlv-hp-dev) ([10.238.158.60]) by orsmga003.jf.intel.com with ESMTP; 19 Aug 2015 21:13:06 -0700 Date: Thu, 20 Aug 2015 12:00:20 +0800 From: Zhiyuan Lv To: intel-gfx@lists.freedesktop.org Message-ID: <20150820040020.GA6213@zlv-hp-dev> Mail-Followup-To: intel-gfx@lists.freedesktop.org, igvt-g@lists.01.org MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) Cc: igvt-g@lists.01.org Subject: [Intel-gfx] [PATCH 6/7] drm/i915: guest i915 notification for Intel-GVTg X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Spam-Status: No, score=-4.8 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP When i915 drivers run inside a VM with Intel-GVTg, some explicit notifications are needed from guest to host device model through PV INFO page write. The notifications include: PPGTT create/destroy EXECLIST create/destroy They are used for the shadow implementation of PPGTT and EXECLIST context. Intel GVT-g needs to write-protect the guest pages of PPGTT and contexts, and clear the write protection when they end their life cycle. Signed-off-by: Zhiyuan Lv Signed-off-by: Zhi Wang --- drivers/gpu/drm/i915/i915_gem_gtt.c | 41 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_lrc.c | 25 ++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 823005c..00dafb0 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -896,6 +896,41 @@ static int gen8_init_scratch(struct i915_address_space *vm) return 0; } +static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt *ppgtt, bool create) +{ + enum vgt_g2v_type msg; + struct drm_device *dev = ppgtt->base.dev; + struct drm_i915_private *dev_priv = dev->dev_private; + unsigned int offset = vgtif_reg(pdp0_lo); + int i; + + if (USES_FULL_48BIT_PPGTT(dev)) { + u64 daddr = px_dma(&ppgtt->pml4); + + I915_WRITE(offset, daddr & 0xffffffff); + I915_WRITE(offset + 4, daddr >> 32); + + msg = (create ? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE : + VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY); + } else { + for (i = 0; i < GEN8_LEGACY_PDPES; i++) { + u64 daddr = i915_page_dir_dma_addr(ppgtt, i); + + I915_WRITE(offset, daddr & 0xffffffff); + I915_WRITE(offset + 4, daddr >> 32); + + offset += 8; + } + + msg = (create ? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE : + VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY); + } + + I915_WRITE(vgtif_reg(g2v_notify), msg); + + return 0; +} + static void gen8_free_scratch(struct i915_address_space *vm) { struct drm_device *dev = vm->dev; @@ -942,6 +977,9 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm) struct i915_hw_ppgtt *ppgtt = container_of(vm, struct i915_hw_ppgtt, base); + if (intel_vgpu_active(vm->dev)) + gen8_ppgtt_notify_vgt(ppgtt, false); + if (!USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) gen8_ppgtt_cleanup_3lvl(ppgtt->base.dev, &ppgtt->pdp); else @@ -1516,6 +1554,9 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt) } } + if (intel_vgpu_active(ppgtt->base.dev)) + gen8_ppgtt_notify_vgt(ppgtt, true); + return 0; free_scratch: diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 4b2ac37..80d424b 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -136,6 +136,7 @@ #include #include "i915_drv.h" #include "intel_mocs.h" +#include "i915_vgpu.h" #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) @@ -2122,6 +2123,22 @@ make_rpcs(struct drm_device *dev) return rpcs; } +static void intel_lr_context_notify_vgt(struct intel_context *ctx, + struct intel_engine_cs *ring, + int msg) +{ + struct drm_device *dev = ring->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + u64 tmp = intel_lr_context_descriptor(ctx, ring); + + I915_WRITE(vgtif_reg(execlist_context_descriptor_lo), + tmp & 0xffffffff); + I915_WRITE(vgtif_reg(execlist_context_descriptor_hi), + tmp >> 32); + + I915_WRITE(vgtif_reg(g2v_notify), msg); +} + static int populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) @@ -2282,6 +2299,10 @@ void intel_lr_context_free(struct intel_context *ctx) ctx->engine[i].ringbuf; struct intel_engine_cs *ring = ringbuf->ring; + if (intel_vgpu_active(ringbuf->ring->dev)) + intel_lr_context_notify_vgt(ctx, ring, + VGT_G2V_EXECLIST_CONTEXT_DESTROY); + if ((ctx == ring->default_context) || (intel_vgpu_active(ring->dev))) { intel_unpin_ringbuffer_obj(ringbuf); @@ -2439,6 +2460,10 @@ int intel_lr_context_deferred_create(struct intel_context *ctx, ctx->engine[ring->id].ringbuf = ringbuf; ctx->engine[ring->id].state = ctx_obj; + if (intel_vgpu_active(dev)) + intel_lr_context_notify_vgt(ctx, ring, + VGT_G2V_EXECLIST_CONTEXT_CREATE); + if (ctx == ring->default_context) lrc_setup_hardware_status_page(ring, ctx_obj); else if (ring->id == RCS && !ctx->rcs_initialized) {