From patchwork Thu Aug 25 09:08:32 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9299027 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1BA16607F0 for ; Thu, 25 Aug 2016 09:09:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0E19F291FD for ; Thu, 25 Aug 2016 09:09:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 02B212922B; Thu, 25 Aug 2016 09:09:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A01A8291FD for ; Thu, 25 Aug 2016 09:09:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0194E6E930; Thu, 25 Aug 2016 09:09:35 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 813B86E91F for ; Thu, 25 Aug 2016 09:09:02 +0000 (UTC) Received: by mail-wm0-x244.google.com with SMTP id q128so6458342wma.1 for ; Thu, 25 Aug 2016 02:09:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=kvgjYPuK4bA8OGqYbtNzkdiYFtgmVDxVIwMiKQL+eL4=; b=bpSpJOgGOYWYgJfVCRH4aGRACKkkDDgNn02aQk/3WKRxP+4djBjuLazC8OW2Z9m1OX snO/Enp6lJDNaTaQ1X2lQjwBJdf10GJ0paxvVuNIPyBlaQMmziD3BChJ5NVor0w9S7gG L09cPnP8MpPImwFwGXXPD585tDxUZBQI85kmJi/9liArLz3dUN0QVKDxxSN/Y4DQmYRz FVyHQHWfFNL5M1QdI5CR7LZics4IYXDEaZLCqDNnFQgLJpK9sjUToAGlebZHilQtuXub MvYjEZzlI1r037oxdlUCfNwdnxhHe61U8PqB2ita2oO/wmdluGe+Gs3BYaIV/xxXYL5x B+lQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=kvgjYPuK4bA8OGqYbtNzkdiYFtgmVDxVIwMiKQL+eL4=; b=CHXI4E9quAo3Vuh2i4h1trkKlkpcOiXhI/AYXbxxG0kLA8DdA6aiMx/enk9v1YH51J Bs9RZ3SnsqZqvcQSszdu/XQzsRSL+NxKGIIOIVVqsEZvg8nUVRaU25iVrCMj5Af6Co+m maCVwMBWKmAfwj9mNz3qoScLtvlXRT7mLSJaIQhPz6K97S0+ko7EUPsNeqSKHFauYoXI F159bvmhcuvyxe3NPf18dSc4SdFPNGQ0RV6o733f9Dzn6l5UEKoH/8QS/cAdVOky3VQs BqsTNTV2gQMlD4Zzp+O3zMgXmZBn1RIpLEpll7IMeONvLorkMu++gBlvwR1vkXpfRKJa Qesw== X-Gm-Message-State: AE9vXwOhRgTpEX0cx1W11B1U09BWbSmZiDV6v9/igrWLS/iChlVgJI4vvhq8GZqHZcFk5Q== X-Received: by 10.28.22.6 with SMTP id 6mr7081531wmw.55.1472116140985; Thu, 25 Aug 2016 02:09:00 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id p83sm14713327wma.18.2016.08.25.02.09.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Aug 2016 02:09:00 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Thu, 25 Aug 2016 10:08:32 +0100 Message-Id: <20160825090839.9952-15-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20160825090839.9952-1-chris@chris-wilson.co.uk> References: <20160825090839.9952-1-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH libdrm 14/15] intel: Allow the client to control implicit synchronisation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The kernel allows implicit synchronisation to be disabled on individual buffers. Use at your own risk. Signed-off-by: Chris Wilson --- intel/intel_bufmgr.h | 2 ++ intel/intel_bufmgr_gem.c | 34 ++++++++++++++++++++++++++++++---- 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/intel/intel_bufmgr.h b/intel/intel_bufmgr.h index a7285b7..f4b9b0e 100644 --- a/intel/intel_bufmgr.h +++ b/intel/intel_bufmgr.h @@ -184,6 +184,8 @@ int drm_intel_gem_bo_map_unsynchronized(drm_intel_bo *bo); int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo); int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo); +void drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo); + void *drm_intel_gem_bo_map__cpu(drm_intel_bo *bo); void *drm_intel_gem_bo_map__gtt(drm_intel_bo *bo); void *drm_intel_gem_bo_map__wc(drm_intel_bo *bo); diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c index 004aeb1..259543f 100644 --- a/intel/intel_bufmgr_gem.c +++ b/intel/intel_bufmgr_gem.c @@ -73,6 +73,8 @@ #define VG(x) #endif +#define EXEC_OBJECT_ASYNC (1 << 6) + #define memclear(s) memset(&s, 0, sizeof(s)) #define DBG(...) do { \ @@ -190,8 +192,11 @@ struct _drm_intel_bo_gem { uint32_t swizzle_mode; unsigned long stride; + unsigned long kflags; + time_t free_time; + /** Array passed to the DRM containing relocation information. */ struct drm_i915_gem_relocation_entry *relocs; /** @@ -570,12 +575,11 @@ drm_intel_add_validate_buffer2(drm_intel_bo *bo, int need_fence) bufmgr_gem->exec2_objects[index].relocation_count = bo_gem->reloc_count; bufmgr_gem->exec2_objects[index].relocs_ptr = (uintptr_t)bo_gem->relocs; bufmgr_gem->exec2_objects[index].alignment = bo->align; - bufmgr_gem->exec2_objects[index].offset = bo_gem->is_softpin ? - bo->offset64 : 0; - bufmgr_gem->exec_bos[index] = bo; - bufmgr_gem->exec2_objects[index].flags = flags; + bufmgr_gem->exec2_objects[index].offset = bo->offset64; + bufmgr_gem->exec2_objects[index].flags = flags | bo_gem->kflags; bufmgr_gem->exec2_objects[index].rsvd1 = 0; bufmgr_gem->exec2_objects[index].rsvd2 = 0; + bufmgr_gem->exec_bos[index] = bo; bufmgr_gem->exec_count++; } @@ -1347,6 +1351,7 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time) for (i = 0; i < bo_gem->softpin_target_count; i++) drm_intel_gem_bo_unreference_locked_timed(bo_gem->softpin_target[i], time); + bo_gem->kflags = 0; bo_gem->reloc_count = 0; bo_gem->used_as_reloc_target = false; bo_gem->softpin_target_count = 0; @@ -2758,6 +2763,27 @@ drm_intel_bufmgr_gem_enable_reuse(drm_intel_bufmgr *bufmgr) } /** + * Disables implicit synchronisation before executing the bo + * + * This will cause rendering corruption unless you correctly manage explicit + * fences for all rendering involving this buffer - including use by others. + * Disabling the implicit serialisation is only required if that serialisation + * is too coarse (for example, you have split the buffer into many + * non-overlapping regions and are sharing the whole buffer between concurrent + * independent command streams). + * + * Note the kernel must advertise support via I915_PARAM_HAS_EXEC_ASYNC or + * subsequent execbufs involving the bo will generate EINVAL. + */ +void +drm_intel_gem_bo_disable_implicit_sync(drm_intel_bo *bo) +{ + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; + + bo_gem->kflags |= EXEC_OBJECT_ASYNC; +} + +/** * Enable use of fenced reloc type. * * New code should enable this to avoid unnecessary fence register