From patchwork Tue Sep 6 06:19:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9315767 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6F16D601C0 for ; Tue, 6 Sep 2016 06:25:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 411B628BDB for ; Tue, 6 Sep 2016 06:25:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 35E5A28BDD; Tue, 6 Sep 2016 06:25:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BEED328BDB for ; Tue, 6 Sep 2016 06:25:54 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8AF1F6E02A; Tue, 6 Sep 2016 06:19:19 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id C510A6E02A for ; Tue, 6 Sep 2016 06:19:18 +0000 (UTC) Received: by mail-wm0-x244.google.com with SMTP id a6so5494563wmc.2 for ; Mon, 05 Sep 2016 23:19:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id; bh=fn3hzvdoaLTxS+leIwvacc8R/Z8Jve9aAB+jGp5NRzo=; b=bYdDi4DAg6Ct05dc9mCpi71hGEG5xk6QJLGMODNVEkjEYgp17h4K0vmv8TB4n5LE8a fb097WIsymTlpxaP9fNHq6u2tXrpRQJEBZkDcCiEg9/pVZC+ZUdRLY6V/GSIepTlXx7V dn6wBs0KBvya4UNh8wyXBnYcS9Y2e+pP/7s0tkzMutVKjisZQgq4ugRfIr2ciXVdHQ8w NHFPMOaP3t1TOP7Llj7yLJg0h4jtOewZVNpPlYUfhu+1MroJAWh/b6cQpXCGUQxdWXH5 c2cdZV4i94WNicGA364VKwB3f/92XHfLHNgc4TRNtUsEXKQXUXCfUIoN29Og8Q60jTwt /rGQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=fn3hzvdoaLTxS+leIwvacc8R/Z8Jve9aAB+jGp5NRzo=; b=mPvUFApzferoV2mjHDr+ihvG5HHy6k2PV1k0FAcJfeI3gbslEF0KMQrdJSKMSWO53M kS/4nX+IVZXDRjBQBae+lmDM5IvIfT/kbi2UD+/OEyZ/9IOVxIvIYFJTX9SJTx8oqnjn sG6QqxQUX16s64sN0ByPs2xg+YSKN9MGUvqw6nFRYMmi4covPt8tOMXITwHbNYwbMz4Q kbPRuIraSeQFBqxa9mBTJov8IWhwJBEox84LKTAR7vrpy6PXFACcmX5OZfCx+8sBhc4j WhBmM6dNuM1GIydhvwr31hIXrNyVMYRmdwAPVoUhmy3KV+1nyS1VKfjrN418PjyxLBLv KCmQ== X-Gm-Message-State: AE9vXwMqEhYny0RZatlXuyej5HrHJYwx3ZtajQBzu2x9SNUP1WLJpl6DVhdVpz63Dav7kw== X-Received: by 10.194.200.198 with SMTP id ju6mr34053570wjc.184.1473142757199; Mon, 05 Sep 2016 23:19:17 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id ks1sm11013604wjb.24.2016.09.05.23.19.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Sep 2016 23:19:15 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Tue, 6 Sep 2016 07:19:12 +0100 Message-Id: <20160906061912.27703-1-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.9.3 Subject: [Intel-gfx] [PATCH] drm/i915: Remove 64b mmio write vfuncs X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP We don't have safe 64-bit mmio writes as they are really split into 2x32-bit writes. This tearing is dangerous as the hardware *will* operate on the intermediate value, requiring great care when assigning. (See, for example, i965_write_fence_reg.) As such we don't currently use them and strongly advise not to us them. Go one step further and remove the 64-bit write vfuncs. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_drv.h | 3 --- drivers/gpu/drm/i915/intel_uncore.c | 9 --------- 2 files changed, 12 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index b0ada4ac6e2d..687367c62ce8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -581,8 +581,6 @@ struct intel_uncore_funcs { uint16_t val, bool trace); void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r, uint32_t val, bool trace); - void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r, - uint64_t val, bool trace); }; struct intel_uncore { @@ -3725,7 +3723,6 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); * act upon the intermediate value, possibly leading to corruption and * machine death. You have been warned. */ -#define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index e9f68cd56e32..a9b6c936aadd 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1018,11 +1018,9 @@ gen5_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, bool __gen5_write(8) __gen5_write(16) __gen5_write(32) -__gen5_write(64) __gen2_write(8) __gen2_write(16) __gen2_write(32) -__gen2_write(64) #undef __gen5_write #undef __gen2_write @@ -1112,23 +1110,18 @@ gen9_write##x(struct drm_i915_private *dev_priv, i915_reg_t reg, u##x val, \ __gen9_write(8) __gen9_write(16) __gen9_write(32) -__gen9_write(64) __chv_write(8) __chv_write(16) __chv_write(32) -__chv_write(64) __gen8_write(8) __gen8_write(16) __gen8_write(32) -__gen8_write(64) __hsw_write(8) __hsw_write(16) __hsw_write(32) -__hsw_write(64) __gen6_write(8) __gen6_write(16) __gen6_write(32) -__gen6_write(64) #undef __gen9_write #undef __chv_write @@ -1158,7 +1151,6 @@ static void vgpu_write##x(struct drm_i915_private *dev_priv, \ __vgpu_write(8) __vgpu_write(16) __vgpu_write(32) -__vgpu_write(64) #undef __vgpu_write #undef VGPU_WRITE_FOOTER @@ -1169,7 +1161,6 @@ do { \ dev_priv->uncore.funcs.mmio_writeb = x##_write8; \ dev_priv->uncore.funcs.mmio_writew = x##_write16; \ dev_priv->uncore.funcs.mmio_writel = x##_write32; \ - dev_priv->uncore.funcs.mmio_writeq = x##_write64; \ } while (0) #define ASSIGN_READ_MMIO_VFUNCS(x) \