From patchwork Fri Sep 9 07:21:01 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9322517 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4357B6077F for ; Fri, 9 Sep 2016 07:21:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2F05F29C4F for ; Fri, 9 Sep 2016 07:21:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 23C5B29C90; Fri, 9 Sep 2016 07:21:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C9CC029C4F for ; Fri, 9 Sep 2016 07:21:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 359836E6CD; Fri, 9 Sep 2016 07:21:31 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id D037D6E6C9 for ; Fri, 9 Sep 2016 07:21:28 +0000 (UTC) Received: by mail-wm0-x242.google.com with SMTP id w12so1396977wmf.1 for ; Fri, 09 Sep 2016 00:21:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:subject:date:message-id:in-reply-to:references; bh=iBBlTw3kbpDZvorcPokMtR0P/f8flhF/PBf9UbDLIzI=; b=C8QF7gVRbivPQ7kVuPOFXHLxLCjwE/BWQ+H1FC4oo/SGDv6ZDx3NAw7SD9gCDan3S2 4K0t3foWY2ZbL0bDtGS5Il9PetjqSEtekLJWpBNBzNJ/HRKPR3frePTnpcuP7Rd6uzqR wSR15DPjP7TyuxVtruiJve8Gqb0+1LUauTqcj3sF6rCbvtQRZSx9+W4GdaYuLvl4HgFF fpyi/tJvtT0c09ktOl4bWyxPQ7SQ0tG7O1jnd8gxPNNYd29LdkZcPLGGFAtZAwxgumqu BK2EHsfLxBjP+2y/KZWS6tLQnqeF2JQOsiUG8+HxCw+P7gicSbQo7Gvg5Ivc4Gv5us6I TZaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:subject:date:message-id :in-reply-to:references; bh=iBBlTw3kbpDZvorcPokMtR0P/f8flhF/PBf9UbDLIzI=; b=DidMsKnqnh5u5AFgL2FsdG3JU2cSEtiIlTlumg1GzZCuAjQJ7nuEtfnCnhuGhg6p/t F3XQjl5uE7F9oWM6M3A9jgCglQXnUvGkuASmZHbbyUhhtJN44nGQBibtWZ6EdnWwszkf KzlCr6rO5Vea9V75oE3orUZf5bR881ZSVqjY3vwk/RvwxOPZCGwlLoC9kTxG5ova2AvL xvh/IVEqipesDXEkLamS4jfszRgd9j9yIkystOPo0k6MZOlVvxdKND+cOCnc6AUQ1HJX mNdEP4b54KfEIwZ1StuREnogREfRC1cHzuokejz/E/vH+KGRqyMH2KIoQdVCnezhqd9K DXmQ== X-Gm-Message-State: AE9vXwPj+z/Riy5jvqLlDfJ1SWPAfw6U+sPDdrg5lLeK7HPH6xoj6kpKdjm4zAEkdN0iKw== X-Received: by 10.28.154.83 with SMTP id c80mr1484127wme.48.1473405687279; Fri, 09 Sep 2016 00:21:27 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id kk6sm1891592wjb.44.2016.09.09.00.21.26 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Sep 2016 00:21:26 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Fri, 9 Sep 2016 08:21:01 +0100 Message-Id: <20160909072107.18861-15-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20160909072107.18861-1-chris@chris-wilson.co.uk> References: <20160909072107.18861-1-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [CI 15/21] drm/i915: Reorder i915_add_request to separate the phases better X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Let's avoid mixing sealing the hardware commands for the request and adding the request to the software tracking. Signed-off-by: Chris Wilson Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_gem_request.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 074fc06ff488..a149310c82ce 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -494,6 +494,8 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) u32 reserved_tail; int ret; + trace_i915_gem_request_add(request); + /* * To ensure that this call will not fail, space for its emissions * should already have been reserved in the ring buffer. Let the ring @@ -517,20 +519,6 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) WARN(ret, "engine->emit_flush() failed: %d!\n", ret); } - trace_i915_gem_request_add(request); - - /* Seal the request and mark it as pending execution. Note that - * we may inspect this state, without holding any locks, during - * hangcheck. Hence we apply the barrier to ensure that we do not - * see a more recent value in the hws than we are tracking. - */ - request->emitted_jiffies = jiffies; - request->previous_seqno = engine->last_submitted_seqno; - engine->last_submitted_seqno = request->fence.seqno; - i915_gem_active_set(&engine->last_request, request); - list_add_tail(&request->link, &engine->request_list); - list_add_tail(&request->ring_link, &ring->request_list); - /* Record the position of the start of the breadcrumb so that * should we detect the updated seqno part-way through the * GPU processing the request, we never over-estimate the @@ -551,6 +539,18 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) "for adding the request (%d bytes)\n", reserved_tail, ret); + /* Seal the request and mark it as pending execution. Note that + * we may inspect this state, without holding any locks, during + * hangcheck. Hence we apply the barrier to ensure that we do not + * see a more recent value in the hws than we are tracking. + */ + request->emitted_jiffies = jiffies; + request->previous_seqno = engine->last_submitted_seqno; + engine->last_submitted_seqno = request->fence.seqno; + i915_gem_active_set(&engine->last_request, request); + list_add_tail(&request->link, &engine->request_list); + list_add_tail(&request->ring_link, &ring->request_list); + i915_gem_mark_busy(engine); local_bh_disable();