| Message ID | 20160930112545.18551-1-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Chris Wilson <chris@chris-wilson.co.uk> writes: > Whilst we reset the GPU, we want to prevent execlists from submitting > new work (which it does via an interrupt handler). To achieve this we > disable the irq (and drain the irq tasklet) around the reset. When we > enable it again afters, the interrupt queue should be empty and we can > reinitialise from a known state without fear of the tasklet running > concurrently. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Mika Kuoppala <mika.kuoppala@intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com> > --- > drivers/gpu/drm/i915/i915_drv.c | 19 +++++++++++++++++++ > drivers/gpu/drm/i915/i915_gem.c | 2 -- > 2 files changed, 19 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 31b2b6300d8d..7ce498898217 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -1728,6 +1728,21 @@ int i915_resume_switcheroo(struct drm_device *dev) > return i915_drm_resume(dev); > } > > +static void disable_engines_irq(struct drm_i915_private *dev_priv) > +{ > + struct intel_engine_cs *engine; > + > + /* Ensure irq handler finishes, and not run again. */ > + disable_irq(dev_priv->drm.irq); > + for_each_engine(engine, dev_priv) > + tasklet_kill(&engine->irq_tasklet); > +} > + > +static void enable_engines_irq(struct drm_i915_private *dev_priv) > +{ > + enable_irq(dev_priv->drm.irq); > +} > + > /** > * i915_reset - reset chip after a hang > * @dev: drm device to reset > @@ -1761,7 +1776,11 @@ void i915_reset(struct drm_i915_private *dev_priv) > error->reset_count++; > > pr_notice("drm/i915: Resetting chip after gpu hang\n"); > + > + disable_engines_irq(dev_priv); > ret = intel_gpu_reset(dev_priv, ALL_ENGINES); > + enable_engines_irq(dev_priv); > + > if (ret) { > if (ret != -ENODEV) > DRM_ERROR("Failed to reset chip: %i\n", ret); > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c > index 1418c1c522cb..0cae8acdf906 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -2581,8 +2581,6 @@ static void i915_gem_reset_engine(struct intel_engine_cs *engine) > struct i915_gem_context *incomplete_ctx; > bool ring_hung; > > - /* Ensure irq handler finishes, and not run again. */ > - tasklet_kill(&engine->irq_tasklet); > if (engine->irq_seqno_barrier) > engine->irq_seqno_barrier(engine); > > -- > 2.9.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 31b2b6300d8d..7ce498898217 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1728,6 +1728,21 @@ int i915_resume_switcheroo(struct drm_device *dev) return i915_drm_resume(dev); } +static void disable_engines_irq(struct drm_i915_private *dev_priv) +{ + struct intel_engine_cs *engine; + + /* Ensure irq handler finishes, and not run again. */ + disable_irq(dev_priv->drm.irq); + for_each_engine(engine, dev_priv) + tasklet_kill(&engine->irq_tasklet); +} + +static void enable_engines_irq(struct drm_i915_private *dev_priv) +{ + enable_irq(dev_priv->drm.irq); +} + /** * i915_reset - reset chip after a hang * @dev: drm device to reset @@ -1761,7 +1776,11 @@ void i915_reset(struct drm_i915_private *dev_priv) error->reset_count++; pr_notice("drm/i915: Resetting chip after gpu hang\n"); + + disable_engines_irq(dev_priv); ret = intel_gpu_reset(dev_priv, ALL_ENGINES); + enable_engines_irq(dev_priv); + if (ret) { if (ret != -ENODEV) DRM_ERROR("Failed to reset chip: %i\n", ret); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1418c1c522cb..0cae8acdf906 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2581,8 +2581,6 @@ static void i915_gem_reset_engine(struct intel_engine_cs *engine) struct i915_gem_context *incomplete_ctx; bool ring_hung; - /* Ensure irq handler finishes, and not run again. */ - tasklet_kill(&engine->irq_tasklet); if (engine->irq_seqno_barrier) engine->irq_seqno_barrier(engine);
Whilst we reset the GPU, we want to prevent execlists from submitting new work (which it does via an interrupt handler). To achieve this we disable the irq (and drain the irq tasklet) around the reset. When we enable it again afters, the interrupt queue should be empty and we can reinitialise from a known state without fear of the tasklet running concurrently. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@intel.com> --- drivers/gpu/drm/i915/i915_drv.c | 19 +++++++++++++++++++ drivers/gpu/drm/i915/i915_gem.c | 2 -- 2 files changed, 19 insertions(+), 2 deletions(-)