From patchwork Fri Sep 30 11:25:45 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9358025 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AE4E060757 for ; Fri, 30 Sep 2016 11:25:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 892EB29FB1 for ; Fri, 30 Sep 2016 11:25:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 793E229FBF; Fri, 30 Sep 2016 11:25:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0D8C129FB1 for ; Fri, 30 Sep 2016 11:25:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3D5876E186; Fri, 30 Sep 2016 11:25:57 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3EE056E186 for ; Fri, 30 Sep 2016 11:25:56 +0000 (UTC) Received: by mail-wm0-x242.google.com with SMTP id b4so3017386wmb.2 for ; Fri, 30 Sep 2016 04:25:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=wkXHcadypNkr2LPu1izfrZAWwkFAZfELflrJd38O4uI=; b=DvzqDOlgNG0DSfmr0EuyrBAzVosql5iQWqSKeFYuv4g597K1P3zKMTFEXm/EoBUhHi MJk4x09IE58q0RHKhU76468RHFkRPN2Pik+OuR3nRd/jWQ8z9cHka+Ws8uPS42Wa1tca 1CJTpHwqO5AnAQymHMwHC7Shvzd+Z1YOJUAWSu9PIfh46GbcjIyWXiwAQW1QwvjxCXzu egdOiWAxiHjXWAkXn5bWngXZ1adO3o4Ean7tYT26bP/8x9ucAGP63Q3ScPKVcjRIrCwT 2W7qt2ySwhZOTRxjZwtOkh4TqxscefcVIsPpexsDCXngkNJu05ZTSWPpuBakCbLcbVoW Sflg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=wkXHcadypNkr2LPu1izfrZAWwkFAZfELflrJd38O4uI=; b=RAdbeA7ubGKybx96b60ZWVEdysE6GXqqHytSLv+co1eUhh6P2IpfvKrf3RqTJfW6Kw ZsqvGDvldinjtRzh82442OlG7ll+x1TJ8DoGUGg594mYXFW+Bflp8JhvIoFLGAYxG52A OnGEUHSmT0ED+ejH8ck1ZnfAb7z7TjV18C70gM3tc+UObFq96qANhBXsUPhhVc3LWjZv Y4ItxxdTufl5W0fwPF7pYS9tFhRS/bCDYGFyrXJVyH1+H3bjqmaA91Ux5SpzGc1cmNei F39f0BKyINCvHbncWE1bWXVOGTUTPHmRgxYK1YxgC1XhnSC6r5dc3hG3OgtxNfLHoRFt Wghg== X-Gm-Message-State: AA6/9Rn4xP3zdvWu2FH87Poj5kM7aBu1htneV0ettTRMLZ2kBqJ7zHPYv5+ZrsEpftu8Cw== X-Received: by 10.28.193.79 with SMTP id r76mr3662152wmf.41.1475234754738; Fri, 30 Sep 2016 04:25:54 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id r195sm3696874wme.10.2016.09.30.04.25.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Sep 2016 04:25:52 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Fri, 30 Sep 2016 12:25:45 +0100 Message-Id: <20160930112545.18551-1-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.9.3 In-Reply-To: <8737kh6be8.fsf@gaia.fi.intel.com> References: <8737kh6be8.fsf@gaia.fi.intel.com> Cc: Mika Kuoppala Subject: [Intel-gfx] [PATCH] drm/i915: Disable irqs across GPU reset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Whilst we reset the GPU, we want to prevent execlists from submitting new work (which it does via an interrupt handler). To achieve this we disable the irq (and drain the irq tasklet) around the reset. When we enable it again afters, the interrupt queue should be empty and we can reinitialise from a known state without fear of the tasklet running concurrently. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.c | 19 +++++++++++++++++++ drivers/gpu/drm/i915/i915_gem.c | 2 -- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 31b2b6300d8d..7ce498898217 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1728,6 +1728,21 @@ int i915_resume_switcheroo(struct drm_device *dev) return i915_drm_resume(dev); } +static void disable_engines_irq(struct drm_i915_private *dev_priv) +{ + struct intel_engine_cs *engine; + + /* Ensure irq handler finishes, and not run again. */ + disable_irq(dev_priv->drm.irq); + for_each_engine(engine, dev_priv) + tasklet_kill(&engine->irq_tasklet); +} + +static void enable_engines_irq(struct drm_i915_private *dev_priv) +{ + enable_irq(dev_priv->drm.irq); +} + /** * i915_reset - reset chip after a hang * @dev: drm device to reset @@ -1761,7 +1776,11 @@ void i915_reset(struct drm_i915_private *dev_priv) error->reset_count++; pr_notice("drm/i915: Resetting chip after gpu hang\n"); + + disable_engines_irq(dev_priv); ret = intel_gpu_reset(dev_priv, ALL_ENGINES); + enable_engines_irq(dev_priv); + if (ret) { if (ret != -ENODEV) DRM_ERROR("Failed to reset chip: %i\n", ret); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1418c1c522cb..0cae8acdf906 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2581,8 +2581,6 @@ static void i915_gem_reset_engine(struct intel_engine_cs *engine) struct i915_gem_context *incomplete_ctx; bool ring_hung; - /* Ensure irq handler finishes, and not run again. */ - tasklet_kill(&engine->irq_tasklet); if (engine->irq_seqno_barrier) engine->irq_seqno_barrier(engine);