From patchwork Fri Oct 14 12:18:30 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9376549 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7DF2E60865 for ; Fri, 14 Oct 2016 12:19:46 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6FBB42A66A for ; Fri, 14 Oct 2016 12:19:46 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 645CC2A66F; Fri, 14 Oct 2016 12:19:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0D22B2A66A for ; Fri, 14 Oct 2016 12:19:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E38316EC43; Fri, 14 Oct 2016 12:19:42 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-lf0-x243.google.com (mail-lf0-x243.google.com [IPv6:2a00:1450:4010:c07::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6F98E6EC32 for ; Fri, 14 Oct 2016 12:19:21 +0000 (UTC) Received: by mail-lf0-x243.google.com with SMTP id x23so12176099lfi.1 for ; Fri, 14 Oct 2016 05:19:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=QGd8HvvZLyHbtcfghBYKLHkwTNwvJ181FyFjBNceqts=; b=RGNcCCJhoHS7wE27DzBh2NEaSbETMXz7CPs794qQ9y2lLnyeUH9Xj0E0yULu8R6Ht0 mqph1Cp9CJHxPBR6l70P/PeTIrVQ6slGa6ENv9A+z2BfhqkiB/rf6b0bjZzO2DMnPwXe NWwxvDqEZq0balOEEExYsz2I8dp0ZX5/MVyUMmtk4D/Bf5UIjkffsqtzf4FXYV+v1GpJ pylAcoRFKfMLJyTLKDTiObXYmhelyJygMS1sSVlSWSMCfpKDcHtiT9UpQlnXPIA3pRfY rxM+IPnFBugm93pio/ywG1JskOKmC7U1S+EIwIG8iiz0Cdxel5+vBA6TrCi78ns/liNZ E0bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=QGd8HvvZLyHbtcfghBYKLHkwTNwvJ181FyFjBNceqts=; b=kQvvf6jIfSXxISpbxkPT6Irbys6Nyc3GDbsxqeMhdHT+CLDz1VcC5pBQmYXAqTB4Kk Fc0SHLhCRToCAF23/M+Qesj7jECGed16WsW+5t0MUQ7WIglEsH9t/fDL9yI93vgC5Qwz xQnfmv2NXSsRG7TKNjyLVTuWDQIsSAUfqZxH98yDKvAJDdkmTsDOzMIvJGaD7GqcvCU9 TAI3WypHZWIofTIHJh/sMWf2XMd6zPTEoYak1vaRtbAoa0sdBwpqTfOShl9dKwrmV4aJ kbMFgY7FuXO9jJxVBuJP/XmB9C8qVojaFhZpRZka6pB3h90RffwZYU3aJDJ+C0ByX3Jv 8jiw== X-Gm-Message-State: AA6/9RnhB6i7pdcUhY6mQsxZ56hexFsXzcdVA/lBzNnJSm/ZrlmI4tAhcSvhID4htjA/Zg== X-Received: by 10.28.93.134 with SMTP id r128mr1500634wmb.13.1476447559460; Fri, 14 Oct 2016 05:19:19 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id rv12sm31513627wjb.29.2016.10.14.05.19.17 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 14 Oct 2016 05:19:17 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Fri, 14 Oct 2016 13:18:30 +0100 Message-Id: <20161014121833.439-39-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20161014121833.439-1-chris@chris-wilson.co.uk> References: <20161014121833.439-1-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH 38/41] drm/i915: Defer setting of global seqno on request to submission X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Defer the assignment of the global seqno on a request to its submission. In the next patch, we will only allocate the global seqno at that time, here we are just enabling the wait-for-submission before wait-for-seqno paths. Signed-off-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_request.c | 29 ++++++++++++++++++++++------- drivers/gpu/drm/i915/intel_breadcrumbs.c | 12 ++++++++---- 2 files changed, 30 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index 5622aaafb1ad..c54fee57c8fb 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -324,14 +324,31 @@ submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state) struct drm_i915_gem_request *request = container_of(fence, typeof(*request), submit); struct intel_engine_cs *engine = request->engine; + struct intel_timeline *timeline; + u32 seqno; if (state != FENCE_COMPLETE) return NOTIFY_DONE; /* Will be called from irq-context when using foreign DMA fences */ - engine->timeline->last_submitted_seqno = request->fence.seqno; + timeline = request->timeline; + seqno = request->fence.seqno; + GEM_BUG_ON(!seqno); + GEM_BUG_ON(i915_seqno_passed(intel_engine_get_seqno(engine), seqno)); + + GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno, seqno)); + request->previous_seqno = timeline->last_submitted_seqno; + timeline->last_submitted_seqno = seqno; + + spin_lock_nested(&request->lock, SINGLE_DEPTH_NESTING); + request->global_seqno = seqno; + if (test_bit(FENCE_FLAG_ENABLE_SIGNAL_BIT, &request->fence.flags)) + intel_engine_enable_signaling(request); + spin_unlock(&request->lock); + + GEM_BUG_ON(!request->global_seqno); engine->emit_breadcrumb(request, request->ring->vaddr + request->postfix); engine->submit_request(request); @@ -427,10 +444,10 @@ i915_gem_request_alloc(struct intel_engine_cs *engine, INIT_LIST_HEAD(&req->active_list); req->i915 = dev_priv; req->engine = engine; - req->global_seqno = req->fence.seqno; req->ctx = i915_gem_context_get(ctx); /* No zalloc, must clear what we need by hand */ + req->global_seqno = 0; req->previous_context = NULL; req->file_priv = NULL; req->batch = NULL; @@ -704,15 +721,13 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) i915_sw_fence_await_sw_fence(&request->submit, &prev->submit, &request->submitq); - GEM_BUG_ON(i915_seqno_passed(timeline->last_submitted_seqno, - request->fence.seqno)); + list_add_tail(&request->link, &timeline->requests); - request->emitted_jiffies = jiffies; - request->previous_seqno = timeline->last_pending_seqno; timeline->last_pending_seqno = request->fence.seqno; i915_gem_active_set(&timeline->last_request, request); - list_add_tail(&request->link, &timeline->requests); + list_add_tail(&request->ring_link, &ring->request_list); + request->emitted_jiffies = jiffies; i915_gem_mark_busy(engine); diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c index 7e65b415c535..594676363056 100644 --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c @@ -77,22 +77,26 @@ static void intel_breadcrumbs_fake_irq(unsigned long data) static void irq_enable(struct intel_engine_cs *engine) { + unsigned long flags; + /* Enabling the IRQ may miss the generation of the interrupt, but * we still need to force the barrier before reading the seqno, * just in case. */ engine->breadcrumbs.irq_posted = true; - spin_lock_irq(&engine->i915->irq_lock); + spin_lock_irqsave(&engine->i915->irq_lock, flags); engine->irq_enable(engine); - spin_unlock_irq(&engine->i915->irq_lock); + spin_unlock_irqrestore(&engine->i915->irq_lock, flags); } static void irq_disable(struct intel_engine_cs *engine) { - spin_lock_irq(&engine->i915->irq_lock); + unsigned long flags; + + spin_lock_irqsave(&engine->i915->irq_lock, flags); engine->irq_disable(engine); - spin_unlock_irq(&engine->i915->irq_lock); + spin_unlock_irqrestore(&engine->i915->irq_lock, flags); engine->breadcrumbs.irq_posted = false; }