From patchwork Thu Oct 27 14:05:16 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9399433 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A232E600BA for ; Thu, 27 Oct 2016 14:05:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 84DB32A2BC for ; Thu, 27 Oct 2016 14:05:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 799492A2F3; Thu, 27 Oct 2016 14:05:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 733DB2A2F8 for ; Thu, 27 Oct 2016 14:05:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8CB566EA74; Thu, 27 Oct 2016 14:05:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id BA4976EA74 for ; Thu, 27 Oct 2016 14:05:33 +0000 (UTC) Received: by mail-wm0-x241.google.com with SMTP id c17so2883598wmc.3 for ; Thu, 27 Oct 2016 07:05:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=cFWr3uAQxSdm5KmCMTsahnJdIuByVxemVeFL59z6V6g=; b=guLWNzpoBAz907x5Rgy6eAHP7m29CKXYBjBk38QnQFbqV8/ASxn5MQV0wkJ9gb/x9T NX4zbsBzLUTmSWiVJN1g092A3fSy8EMfOv5YtBgcEE2DB2QZczy6H3rwuRHPSKM2GN5/ 79bRmoAi869LrM3vxhAJXk1uB9W9Q3I3ldRVDHlo779Yq5Z6HI797r4AOQzfUC54qycs bYKEGLFD5+zjqR74pEAcLv/ku21iQndlPND66YbGPizhzNhPEOLgr6pAkBcvcLvsROHF 4Sx1wq9NxJY5yQyBIFSeG9dzwmwFLuGqwQdkQNG/eHxv09tGAgWL4Mxpe9LJQ6zTHG9D +L/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=cFWr3uAQxSdm5KmCMTsahnJdIuByVxemVeFL59z6V6g=; b=RmYsBwuGxr3yJ7KUjGQo2o+0i5Qhr6u5WdjRsaFSapvfGyXpu1RWdScGa1hAtNOqHw Na5nTMJtOyPYj8B3dV4+ciOidu7miUrxEUkMtTSjXm8V1JsuVaPMzJx1JL6VI+L4oMy6 sAA21mgWgreZ9V8KmFHGBidB7OL8O3pCaa3dgpJ/GLxqgoiF4VC55w15wtMMMHeAWi6l XVBeuOoM5cHqF9E98ZLiplRDKMazF9dnEpFxLWkKM6+vVeLardc62QWtRjtCvsBzzCRa 3Mv1Cfjp45LKvl7YWyIMO8TlFr/kGrMzjOadp6kY8G3OPy5oLkauEbZLc+z1fhiSwelo SoHg== X-Gm-Message-State: ABUngvfjNKrXY16hmh6oo35K8EzHmUWgP6n+rQelNexIp+Z1BqObiQHzroMmnr6fULq9TQ== X-Received: by 10.28.26.75 with SMTP id a72mr7751854wma.36.1477577132268; Thu, 27 Oct 2016 07:05:32 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id vf8sm8684161wjc.27.2016.10.27.07.05.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 27 Oct 2016 07:05:31 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Thu, 27 Oct 2016 15:05:16 +0100 Message-Id: <20161027140516.22435-9-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161027140516.22435-1-chris@chris-wilson.co.uk> References: <20161027000348.4641-1-chris@chris-wilson.co.uk> <20161027140516.22435-1-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH v2 9/9] drm/i915/scheduler: Support user-defined priorities X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Use a priority stored in the context as the initial value when submitting a request. This allows us to change the default priority on a per-context basis, allowing different contexts to be favoured with GPU time at the expense of lower importance work. The user can adjust the context's priority via I915_CONTEXT_PARAM_PRIORITY, with more positive values being higher priority (they will be serviced earlier, after their dependencies have been resolved). Any prerequisite work for an execbuf will have its priority raised to match the new request as required. Normal users can specify any value in the range of -1023 to 0 [default], i.e. they can reduce the priority of their workloads (and temporarily boost it back to normal if so desired). Privileged users can specify any value in the range of -1023 to 1023, [default is 0], i.e. they can raise their priority above all overs and so potentially starve the system. Note that the existing schedulers are not fair, nor load balancing, the execution is strictly by priority on a first-come, first-served basis, and the driver may choose to boost some requests above the range available to users. This priority was originally based around nice(2), but evolved to allow clients to adjust their priority within a small range, and allow for a privileged high priority range. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_context.c | 21 +++++++++++++++++++++ drivers/gpu/drm/i915/i915_gem_request.c | 2 +- include/uapi/drm/i915_drm.h | 3 +++ 4 files changed, 26 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index e3b4412d0241..2da5ecad1f35 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -948,6 +948,7 @@ struct i915_gem_context { /* Unique identifier for this context, used by the hw for tracking */ unsigned int hw_id; u32 user_handle; + int priority; /* greater priorities are serviced first */ u32 ggtt_alignment; diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 34daef828dca..8df216eba490 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -476,6 +476,7 @@ int i915_gem_context_init(struct drm_device *dev) return PTR_ERR(ctx); } + ctx->priority = -I915_PRIORITY_MAX; /* lowest priority; idle task */ dev_priv->kernel_context = ctx; DRM_DEBUG_DRIVER("%s context support initialized\n", @@ -1095,6 +1096,9 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, case I915_CONTEXT_PARAM_NO_ERROR_CAPTURE: args->value = !!(ctx->flags & CONTEXT_NO_ERROR_CAPTURE); break; + case I915_CONTEXT_PARAM_PRIORITY: + args->value = ctx->priority; + break; default: ret = -EINVAL; break; @@ -1150,6 +1154,23 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, ctx->flags &= ~CONTEXT_NO_ERROR_CAPTURE; } break; + + case I915_CONTEXT_PARAM_PRIORITY: + { + int priority = args->value; + + if (args->size) + ret = -EINVAL; + else if (priority >= I915_PRIORITY_MAX || + priority <= -I915_PRIORITY_MAX) + ret = -EINVAL; + else if (priority > 0 && !capable(CAP_SYS_ADMIN)) + ret = -EPERM; + else + ctx->priority = priority; + } + break; + default: ret = -EINVAL; break; diff --git a/drivers/gpu/drm/i915/i915_gem_request.c b/drivers/gpu/drm/i915/i915_gem_request.c index fabd29fde175..4bfccb3d0c2c 100644 --- a/drivers/gpu/drm/i915/i915_gem_request.c +++ b/drivers/gpu/drm/i915/i915_gem_request.c @@ -844,7 +844,7 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches) * run at the earliest possible convenience. */ if (engine->schedule) - engine->schedule(request, 0); + engine->schedule(request, request->ctx->priority); local_bh_disable(); i915_sw_fence_commit(&request->submit); diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index f51d429feaae..9fa5eee64f6b 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -404,6 +404,8 @@ typedef struct drm_i915_irq_wait { /* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution * priorities and the driver will attempt to execute batches in priority order. + * The initial priority for each batch is supplied by the context and is + * controlled via I915_CONTEXT_PARAM_PRIORITY. */ #define I915_PARAM_HAS_SCHEDULER 43 @@ -1283,6 +1285,7 @@ struct drm_i915_gem_context_param { #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 +#define I915_CONTEXT_PARAM_PRIORITY 0x5 __u64 value; };