From patchwork Mon Nov 14 08:57:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9426879 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 20B6C6047D for ; Mon, 14 Nov 2016 08:57:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1256A2884D for ; Mon, 14 Nov 2016 08:57:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0775E28853; Mon, 14 Nov 2016 08:57:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 95D3D2884D for ; Mon, 14 Nov 2016 08:57:46 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AB09C6E376; Mon, 14 Nov 2016 08:57:40 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id 47E7A6E369 for ; Mon, 14 Nov 2016 08:57:22 +0000 (UTC) Received: by mail-wm0-x243.google.com with SMTP id a20so13343392wme.2 for ; Mon, 14 Nov 2016 00:57:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=wnzLvDHcK+RWOoKZOCqu7OXzwz1JU0ksrtZH0f9xHWw=; b=LfN9YppSXWsVrDGOVCzo8giVovT2GiHcWQXaiF/tmzBtTohDQ4c3LSV6lM3r/PGC+i B3teb0yphwfoDuB41uCqPGWG++yurCMmkwwpfXDH8dd91Eexhh3YK+foZcFcysqZOF4K PHTi3qV+Ec0/xSLwC9hVCtiEIvgRMMf1lw8img1auPJPBEi61dG08VoXgzj1UEbL1fE/ 9zSMdA90pGiW4F+yTaizvMZin5rtK+2PMRHKGCI/Gu66S7ZosnvbMfnQpR9UHYQNwIJy Ow0V1oZRtMpyozF5ecfMjjMTZK+vLJIyto++OGxh/yvhAw2m4dYpDwbijX323QsqVrIS nR9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=wnzLvDHcK+RWOoKZOCqu7OXzwz1JU0ksrtZH0f9xHWw=; b=Y7cr793uQUtrqUQMLoNqKyRDUfekLdnxGYTerlfOQQSp9+ues9GQ+zimcvbTLyRXiR AkPxOAALiS6URK6bv+tO/Y9vovyxqJ5W/Y1upxyNWwKqCyGUqOCbJbuf6znx1q5lquuk Df5oQis70TLBopv2AJ9YE0zvWeR951WtSwwWWwXmR34UDEoGLZAC6gSXwh7AJWWjIlhg Vi1OVQvcVABUm35mWwav8qq2RIde5XYbfvzMDWv4u6EChrrwiRUgNQ5GWEwT/iWZRHuu 2LqSOrhh+3LAABOJ+4qlrB3PGAhXmvgPXi745Sij8Hh4AT5ncdLBAhFx9adm+mEbtNaJ r/hg== X-Gm-Message-State: ABUngvfziTrlDbkwzwfOpLxQe5WkGw7zyBrHjWJLTczjOzk/8xsAypOoVCe+2Z0Q5frPjQ== X-Received: by 10.28.23.137 with SMTP id 131mr9007393wmx.121.1479113840363; Mon, 14 Nov 2016 00:57:20 -0800 (PST) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id d64sm34871433wmh.3.2016.11.14.00.57.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Nov 2016 00:57:19 -0800 (PST) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Mon, 14 Nov 2016 08:57:00 +0000 Message-Id: <20161114085703.16540-11-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20161114085703.16540-1-chris@chris-wilson.co.uk> References: <20161107135950.28861-1-chris@chris-wilson.co.uk> <20161114085703.16540-1-chris@chris-wilson.co.uk> Subject: [Intel-gfx] [PATCH v3 11/14] HACK drm/i915/scheduler: emulate a scheduler for guc X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This emulates execlists on top of the GuC in order to defer submission of requests to the hardware. This deferral allows time for high priority requests to gazump their way to the head of the queue, however it nerfs the GuC by converting it back into a simple execlist (where the CPU has to wake up after every request to feed new commands into the GuC). --- drivers/gpu/drm/i915/i915_guc_submission.c | 85 +++++++++++++++++++++++++----- drivers/gpu/drm/i915/i915_irq.c | 4 +- drivers/gpu/drm/i915/intel_lrc.c | 3 -- 3 files changed, 76 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 4462112725ef..088f5a99ecfc 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -469,7 +469,7 @@ int i915_guc_wq_reserve(struct drm_i915_gem_request *request) u32 freespace; int ret; - spin_lock(&gc->wq_lock); + spin_lock_irq(&gc->wq_lock); freespace = CIRC_SPACE(gc->wq_tail, desc->head, gc->wq_size); freespace -= gc->wq_rsvd; if (likely(freespace >= wqi_size)) { @@ -479,7 +479,7 @@ int i915_guc_wq_reserve(struct drm_i915_gem_request *request) gc->no_wq_space++; ret = -EAGAIN; } - spin_unlock(&gc->wq_lock); + spin_unlock_irq(&gc->wq_lock); return ret; } @@ -491,9 +491,9 @@ void i915_guc_wq_unreserve(struct drm_i915_gem_request *request) GEM_BUG_ON(READ_ONCE(gc->wq_rsvd) < wqi_size); - spin_lock(&gc->wq_lock); + spin_lock_irq(&gc->wq_lock); gc->wq_rsvd -= wqi_size; - spin_unlock(&gc->wq_lock); + spin_unlock_irq(&gc->wq_lock); } /* Construct a Work Item and append it to the GuC's Work Queue */ @@ -644,7 +644,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq) rq->previous_context = engine->last_context; engine->last_context = rq->ctx; - i915_gem_request_submit(rq); + __i915_gem_request_submit(rq); spin_lock(&client->wq_lock); guc_wq_item_append(client, rq); @@ -665,6 +665,70 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq) spin_unlock(&client->wq_lock); } +static bool i915_guc_dequeue(struct intel_engine_cs *engine) +{ + struct execlist_port *port = engine->execlist_port; + struct drm_i915_gem_request *last = port[0].request; + unsigned long flags; + struct rb_node *rb; + bool submit = false; + + spin_lock_irqsave(&engine->timeline->lock, flags); + rb = engine->execlist_first; + while (rb) { + struct drm_i915_gem_request *cursor = + rb_entry(rb, typeof(*cursor), priotree.node); + + if (last && cursor->ctx != last->ctx) { + if (port != engine->execlist_port) + break; + + i915_gem_request_assign(&port->request, last); + dma_fence_enable_sw_signaling(&last->fence); + port++; + } + + rb = rb_next(rb); + rb_erase(&cursor->priotree.node, &engine->execlist_queue); + RB_CLEAR_NODE(&cursor->priotree.node); + cursor->priotree.priority = INT_MAX; + + i915_guc_submit(cursor); + last = cursor; + submit = true; + } + if (submit) { + i915_gem_request_assign(&port->request, last); + dma_fence_enable_sw_signaling(&last->fence); + engine->execlist_first = rb; + } + spin_unlock_irqrestore(&engine->timeline->lock, flags); + + return submit; +} + +static void i915_guc_irq_handler(unsigned long data) +{ + struct intel_engine_cs *engine = (struct intel_engine_cs *)data; + struct execlist_port *port = engine->execlist_port; + struct drm_i915_gem_request *rq; + bool submit; + + do { + rq = port[0].request; + while (rq && i915_gem_request_completed(rq)) { + i915_gem_request_put(rq); + rq = port[1].request; + port[0].request = rq; + port[1].request = NULL; + } + + submit = false; + if (!port[1].request) + submit = i915_guc_dequeue(engine); + } while (submit); +} + /* * Everything below here is concerned with setup & teardown, and is * therefore not part of the somewhat time-critical batch-submission @@ -1531,16 +1595,13 @@ int i915_guc_submission_enable(struct drm_i915_private *dev_priv) /* Take over from manual control of ELSP (execlists) */ for_each_engine(engine, dev_priv, id) { - engine->submit_request = i915_guc_submit; - engine->schedule = NULL; + tasklet_init(&engine->irq_tasklet, + i915_guc_irq_handler, + (unsigned long)engine); /* Replay the current set of previously submitted requests */ - list_for_each_entry(request, - &engine->timeline->requests, link) { + list_for_each_entry(request, &engine->timeline->requests, link) client->wq_rsvd += sizeof(struct guc_wq_item); - if (i915_sw_fence_done(&request->submit)) - i915_guc_submit(request); - } } return 0; diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index cb8a75f6ca16..18dce4c66d56 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1341,8 +1341,10 @@ static void snb_gt_irq_handler(struct drm_i915_private *dev_priv, static __always_inline void gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift) { - if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) + if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) { + tasklet_schedule(&engine->irq_tasklet); notify_ring(engine); + } if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) tasklet_schedule(&engine->irq_tasklet); } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index d13a335ad83a..ffab255e55a7 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1425,9 +1425,6 @@ static void reset_common_ring(struct intel_engine_cs *engine, request->ring->last_retired_head = -1; intel_ring_update_space(request->ring); - if (i915.enable_guc_submission) - return; - /* Catch up with any missed context-switch interrupts */ I915_WRITE(RING_CONTEXT_STATUS_PTR(engine), _MASKED_FIELD(0xffff, 0)); if (request->ctx != port[0].request->ctx) {