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[86.3.57.50]) by smtp.gmail.com with ESMTPSA id q145sm14832978pfq.22.2016.11.14.12.51.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 14 Nov 2016 12:51:57 -0800 (PST) From: Robert Bragg To: intel-gfx@lists.freedesktop.org Date: Mon, 14 Nov 2016 20:51:17 +0000 Message-Id: <20161114205122.10742-9-robert@sixbynine.org> X-Mailer: git-send-email 2.10.1 In-Reply-To: <20161114205122.10742-1-robert@sixbynine.org> References: <20161114205122.10742-1-robert@sixbynine.org> Subject: [Intel-gfx] [PATCH igt v4 08/13] igt/gem_exec_parse: make basic-rejected version agnostic X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This adapts the basic-rejected test to focus on invalid commands that will result in an EINVAL errno being returned to userspace even with the upcoming version 8 parser change to stop reporting access violations as EINVAL errors. Signed-off-by: Robert Bragg Reviewed-by: Matthew Auld --- tests/gem_exec_parse.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/tests/gem_exec_parse.c b/tests/gem_exec_parse.c index 6dc9998..03e4d0e 100644 --- a/tests/gem_exec_parse.c +++ b/tests/gem_exec_parse.c @@ -42,6 +42,10 @@ #define HSW_CS_GPR0 HSW_CS_GPR(0) #define HSW_CS_GPR1 HSW_CS_GPR(1) +/* To help craft commands known to be invalid across all engines */ +#define INSTR_CLIENT_SHIFT 29 +#define INSTR_INVALID_CLIENT 0x7 + #define MI_LOAD_REGISTER_REG (0x2a << 23) #define MI_STORE_REGISTER_MEM (0x24 << 23) #define MI_ARB_ON_OFF (0x8 << 23) @@ -411,33 +415,38 @@ igt_main } igt_subtest("basic-rejected") { - uint32_t arb_on_off[] = { - MI_ARB_ON_OFF, + uint32_t invalid_cmd[] = { + INSTR_INVALID_CLIENT << INSTR_CLIENT_SHIFT, MI_BATCH_BUFFER_END, }; - uint32_t display_flip[] = { - MI_DISPLAY_FLIP, - 0, 0, 0, + uint32_t invalid_set_context[] = { + MI_SET_CONTEXT | 32, /* invalid length */ MI_BATCH_BUFFER_END, - 0 }; exec_batch(fd, handle, - arb_on_off, sizeof(arb_on_off), + invalid_cmd, sizeof(invalid_cmd), I915_EXEC_RENDER, -EINVAL); exec_batch(fd, handle, - arb_on_off, sizeof(arb_on_off), + invalid_cmd, sizeof(invalid_cmd), I915_EXEC_BSD, -EINVAL); + if (gem_has_blt(fd)) { + exec_batch(fd, handle, + invalid_cmd, sizeof(invalid_cmd), + I915_EXEC_BLT, + -EINVAL); + } if (gem_has_vebox(fd)) { exec_batch(fd, handle, - arb_on_off, sizeof(arb_on_off), + invalid_cmd, sizeof(invalid_cmd), I915_EXEC_VEBOX, -EINVAL); } + exec_batch(fd, handle, - display_flip, sizeof(display_flip), - I915_EXEC_BLT, + invalid_set_context, sizeof(invalid_set_context), + I915_EXEC_RENDER, -EINVAL); }