From patchwork Fri Jan 20 10:15:09 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9527909 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9958960459 for ; Fri, 20 Jan 2017 10:15:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8A29B26E91 for ; Fri, 20 Jan 2017 10:15:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7E9C62863A; Fri, 20 Jan 2017 10:15:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 83B6F26E91 for ; Fri, 20 Jan 2017 10:15:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9EF826EB70; Fri, 20 Jan 2017 10:15:15 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id 066136EB70 for ; Fri, 20 Jan 2017 10:15:14 +0000 (UTC) Received: by mail-wm0-x243.google.com with SMTP id c85so5542582wmi.1 for ; Fri, 20 Jan 2017 02:15:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=hOoHM/51zAr6g4g4i0ZMV16JA+ADlUpx0s72sX+4xOM=; b=I+4ipxd6uhAQPqWsRtT/Ked1NYjybLbjPQ+AAewwNnvuraCov94wEFBSfxyP576HYO 6vnEe9/+mldfHG3QMGOr5Mpz2oMfk8hMKOv7dBI2JgxfAFfx7JGHpjiyGhYdvivX5Hjh xlMYbLVjXx7AtsS+6HeQJJDB1S75t/oV7C1Ce+YutXnVUmJXHsEdRt0imBffXjHGo1ak GKMfCSUYGKyYqCmpV8b8F/fmLdw0A6ovepb/62US7ZLXSeezkx4fWp2S3xC0hOrCHjCE P9qd6EGA5Nczo+qcZevu0hVy7yIiIsPQRnB5++ShbJseQY2uHo6vd5pdSRRPmAgIDrfE Xcfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=hOoHM/51zAr6g4g4i0ZMV16JA+ADlUpx0s72sX+4xOM=; b=sgjOxbTK8ApQ3m545P9QqwfmhLghhL1CvSRurbjO9UBMjUD2gcEM16bnDtrEnW7kev Qr3RX1MaoQH3oYpH6DlU4tjNyp8JvH5A8abqoLSGxeEht7W9nyRxgnQQLv4guhKLVvTL LAqfo+D3gY950lftR25i9FaPO6uL7YieKlrehyhrrG6IcipqkW1/jLAYLnswXxG5Q15/ AYQOJOS5rKAzB4Gep7TLSImQgqYHWpaS2u0I/VWZ5+tBH8+R5a7QO3bKq+k6VUz+ZEbD dTaM3KLYYwmf7uJ9eFzQQ1k6G2rxw4ZBKIyV9gdtM3I25SkDF6b/+j78306Fi7NtaK/f +b6g== X-Gm-Message-State: AIkVDXKue9r0W9dpUgTQRpNQbUsAqrw2GUFn/YzcNqmh70QZ2Rau51esv4/tQShLydkriw== X-Received: by 10.28.52.210 with SMTP id b201mr2518357wma.130.1484907312285; Fri, 20 Jan 2017 02:15:12 -0800 (PST) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id g75sm5086771wme.5.2017.01.20.02.15.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 20 Jan 2017 02:15:11 -0800 (PST) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Fri, 20 Jan 2017 10:15:09 +0000 Message-Id: <20170120101509.6886-1-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 Subject: [Intel-gfx] [RFC] drm/i915: Skip BSW display interrupt checks if we have a GT interrupt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP GT interrupts are very, very frequent as they are used for submitting every request to the hardware (thanks be to execlists). Given their prevalence and the comparity rarity of display interrupts, if we do receive an IRQ and we process a GT interrupt skip the *unconditional* checking of the display pipes. This gives a 20% improvement in *walltime* of GEM execution tests on my Braswell nuc. Signed-off-by: Chris Wilson Cc: Ville Syrjälä Cc: Tvrtko Ursulin --- drivers/gpu/drm/i915/i915_irq.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 7aaa0121c2e9..071e0fa21ca0 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1743,16 +1743,17 @@ static bool intel_pipe_handle_vblank(struct drm_i915_private *dev_priv, return ret; } -static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv, +static bool valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv, u32 iir, u32 pipe_stats[I915_MAX_PIPES]) { + bool active = false; int pipe; spin_lock(&dev_priv->irq_lock); if (!dev_priv->display_irqs_enabled) { spin_unlock(&dev_priv->irq_lock); - return; + return false; } for_each_pipe(dev_priv, pipe) { @@ -1797,8 +1798,12 @@ static void valleyview_pipestat_irq_ack(struct drm_i915_private *dev_priv, if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS | PIPESTAT_INT_STATUS_MASK)) I915_WRITE(reg, pipe_stats[pipe]); + + active = true; } spin_unlock(&dev_priv->irq_lock); + + return active; } static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, @@ -1966,12 +1971,19 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) u32 gt_iir[4] = {}; u32 pipe_stats[I915_MAX_PIPES] = {}; u32 hotplug_status = 0; + bool any_pipe_stats = false; u32 ier = 0; master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; - iir = I915_READ(VLV_IIR); + I915_WRITE(GEN8_MASTER_IRQ, 0); + + if (gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir)) { + ret = IRQ_HANDLED; + goto skip_display; + } - if (master_ctl == 0 && iir == 0) + iir = I915_READ(VLV_IIR); + if (iir == 0) break; ret = IRQ_HANDLED; @@ -1989,18 +2001,17 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) * don't end up clearing all the VLV_IIR and GEN8_MASTER_IRQ_CONTROL * bits this time around. */ - I915_WRITE(GEN8_MASTER_IRQ, 0); ier = I915_READ(VLV_IER); I915_WRITE(VLV_IER, 0); - gen8_gt_irq_ack(dev_priv, master_ctl, gt_iir); if (iir & I915_DISPLAY_PORT_INTERRUPT) hotplug_status = i9xx_hpd_irq_ack(dev_priv); /* Call regardless, as some status bits might not be * signalled in iir */ - valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats); + any_pipe_stats = + valleyview_pipestat_irq_ack(dev_priv, iir, pipe_stats); /* * VLV_IIR is single buffered, and reflects the level @@ -2010,6 +2021,8 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) I915_WRITE(VLV_IIR, iir); I915_WRITE(VLV_IER, ier); + +skip_display: I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); POSTING_READ(GEN8_MASTER_IRQ); @@ -2018,7 +2031,8 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg) if (hotplug_status) i9xx_hpd_irq_handler(dev_priv, hotplug_status); - valleyview_pipestat_irq_handler(dev_priv, pipe_stats); + if (any_pipe_stats) + valleyview_pipestat_irq_handler(dev_priv, pipe_stats); } while (0); enable_rpm_wakeref_asserts(dev_priv);