| Message ID | 20170123121429.13399-2-chris@chris-wilson.co.uk (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Jan 23, 2017 at 12:14:26PM +0000, Chris Wilson wrote: > Mark when we run the execlist tasklet following the interrupt, so we > don't probe a potentially initialised register when submitting the s/initialised/uninitialised/! -Chris
Chris Wilson <chris@chris-wilson.co.uk> writes: > Mark when we run the execlist tasklet following the interrupt, so we > don't probe a potentially initialised register when submitting the > contexts multiple times. > > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> > --- > drivers/gpu/drm/i915/i915_irq.c | 7 +++++-- > drivers/gpu/drm/i915/intel_lrc.c | 3 ++- > drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + > 3 files changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 6fefc34ef602..42be116dd33d 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1349,8 +1349,11 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift) > { > if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) > notify_ring(engine); > - if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) > - tasklet_schedule(&engine->irq_tasklet); > + > + if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) { > + set_bit(IRQ_CTX_SWITCH, &engine->irq_tasklet.state); > + tasklet_hi_schedule(&engine->irq_tasklet); > + } > } > > static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv, > diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c > index 873c3a8a580b..d2adfc77260a 100644 > --- a/drivers/gpu/drm/i915/intel_lrc.c > +++ b/drivers/gpu/drm/i915/intel_lrc.c > @@ -577,7 +577,7 @@ static void intel_lrc_irq_handler(unsigned long data) > > intel_uncore_forcewake_get(dev_priv, engine->fw_domains); > > - if (!execlists_elsp_idle(engine)) { > + while (test_and_clear_bit(IRQ_CTX_SWITCH, &engine->irq_tasklet.state)) { > u32 __iomem *csb_mmio = > dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); > u32 __iomem *buf = > @@ -1346,6 +1346,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine) > DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); > > /* After a GPU reset, we may have requests to replay */ > + clear_bit(IRQ_CTX_SWITCH, &engine->irq_tasklet.state); > if (!execlists_elsp_idle(engine)) { > engine->execlist_port[0].count = 0; > engine->execlist_port[1].count = 0; > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h > index 34cdbb6350a8..c63f39d47fdd 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.h > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h > @@ -373,6 +373,7 @@ struct intel_engine_cs { > > /* Execlists */ > struct tasklet_struct irq_tasklet; > +#define IRQ_CTX_SWITCH (BITS_PER_LONG - 1) /* TASKLET_STATE_USER */ Looking at the tasklet code, TASKLET_STATE_USER would be a good idea. However until we have one, I think we need to avoid piggybacking on tasklet state. -Mika > struct execlist_port { > struct drm_i915_gem_request *request; > unsigned int count; > -- > 2.11.0
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 6fefc34ef602..42be116dd33d 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1349,8 +1349,11 @@ gen8_cs_irq_handler(struct intel_engine_cs *engine, u32 iir, int test_shift) { if (iir & (GT_RENDER_USER_INTERRUPT << test_shift)) notify_ring(engine); - if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) - tasklet_schedule(&engine->irq_tasklet); + + if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift)) { + set_bit(IRQ_CTX_SWITCH, &engine->irq_tasklet.state); + tasklet_hi_schedule(&engine->irq_tasklet); + } } static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 873c3a8a580b..d2adfc77260a 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -577,7 +577,7 @@ static void intel_lrc_irq_handler(unsigned long data) intel_uncore_forcewake_get(dev_priv, engine->fw_domains); - if (!execlists_elsp_idle(engine)) { + while (test_and_clear_bit(IRQ_CTX_SWITCH, &engine->irq_tasklet.state)) { u32 __iomem *csb_mmio = dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); u32 __iomem *buf = @@ -1346,6 +1346,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine) DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); /* After a GPU reset, we may have requests to replay */ + clear_bit(IRQ_CTX_SWITCH, &engine->irq_tasklet.state); if (!execlists_elsp_idle(engine)) { engine->execlist_port[0].count = 0; engine->execlist_port[1].count = 0; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 34cdbb6350a8..c63f39d47fdd 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -373,6 +373,7 @@ struct intel_engine_cs { /* Execlists */ struct tasklet_struct irq_tasklet; +#define IRQ_CTX_SWITCH (BITS_PER_LONG - 1) /* TASKLET_STATE_USER */ struct execlist_port { struct drm_i915_gem_request *request; unsigned int count;
Mark when we run the execlist tasklet following the interrupt, so we don't probe a potentially initialised register when submitting the contexts multiple times. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_irq.c | 7 +++++-- drivers/gpu/drm/i915/intel_lrc.c | 3 ++- drivers/gpu/drm/i915/intel_ringbuffer.h | 1 + 3 files changed, 8 insertions(+), 3 deletions(-)