From patchwork Tue Jan 24 11:00:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9534899 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C96EA6042D for ; Tue, 24 Jan 2017 11:00:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC28126CFF for ; Tue, 24 Jan 2017 11:00:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B145626D08; Tue, 24 Jan 2017 11:00:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5B25326CFF for ; Tue, 24 Jan 2017 11:00:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C08406E743; Tue, 24 Jan 2017 11:00:17 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id B63956E743 for ; Tue, 24 Jan 2017 11:00:15 +0000 (UTC) Received: by mail-wm0-x242.google.com with SMTP id r126so33773375wmr.3 for ; Tue, 24 Jan 2017 03:00:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=UpliKBoaL0muVVGfwY147DhEvY3ALP7hKZ7BqiZW3F0=; b=iuPbAW4akVU5FguMi9RBUj2gBK/uzfYKi23/s0MrvOm1s4j1I3pr98c62seAT1lTqm tD9vmvq47B/8WpaWk5rCfeolkxOzJ+p+YNcfPFmI8bMjEKPV2xhMFIOeRdGAjJo2Bjg9 e1XRxb39R7EDp1axevRVhBiGwJHFuf7bmnU0GqG3U2tD5n5dIyk3F3OM2FNRsykX7/eo RcXVFZf8weuAlnfspZhatlmvTIjiS/YVWeVrmvEAomE3B9UjIxYoUv2zeFOU+RmVD7Cz 3KqpGuvmwAHi3esLyBlOYlTgbp6h5bIlup1ykcSwa4FQNNpeMDogr/wzUYjjXBqPOOWz odKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=UpliKBoaL0muVVGfwY147DhEvY3ALP7hKZ7BqiZW3F0=; b=t+zfy7wxmVo7JGLvBqWfaAQ4mPr0BEhuzVPjoEgcz5A93ssYJjfHkvTFUw9nOLMzt6 MehOtwzEwfsA0olTs6n9CZuIArgTbGjxf15EGQhUgSDstFW+15J4KUKG/lQkBK93QTvE IAieJTQPrbQEv31jr9wiN12zdIQWdTA27FPNoiVw7DqN2WLGUF0oeuUveohzcRIE87Uu 5S8jUxZL2NC+n7AwbewXpFE0dZY4uFLIzOmFP3C/iU7uUgZqiEVeqR4pUTdQ8Ixr2T1K xd20zrtQJOdQglaUepJl7JNT6IG0MXNqoBY9eSb1fxy5lHmdaPnbEYaTk+5fgdgcL3i/ bmKQ== X-Gm-Message-State: AIkVDXIwjwkvHeiihXyyzY0uITU9igOAk8lSTRq1YbZqduM4nxV9wKBOG8hbiiafgqXf1w== X-Received: by 10.28.220.135 with SMTP id t129mr19447451wmg.38.1485255614065; Tue, 24 Jan 2017 03:00:14 -0800 (PST) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id x69sm11857573wma.15.2017.01.24.03.00.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 24 Jan 2017 03:00:13 -0800 (PST) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Tue, 24 Jan 2017 11:00:04 +0000 Message-Id: <20170124110009.28947-3-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170124110009.28947-1-chris@chris-wilson.co.uk> References: <20170124110009.28947-1-chris@chris-wilson.co.uk> Cc: Mika Kuoppala Subject: [Intel-gfx] [PATCH v3 3/8] drm/i915: Move breadcrumbs irq_posted up a level to engine X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP In the next patch, we will use the irq_posted technique for another engine interrupt, rather than use two members for the atomic updates, we can use two bits of one instead. First, we need to update the breadcrumbs to use the new common engine->irq_posted. Signed-off-by: Chris Wilson Cc: Mika Kuoppala Cc: Tvrtko Ursulin irq_seqno_barrier && rcu_access_pointer(engine->breadcrumbs.irq_seqno_bh) == current && - cmpxchg_relaxed(&engine->breadcrumbs.irq_posted, 1, 0)) { + test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) { struct task_struct *tsk; /* The ordering of irq_posted versus applying the barrier diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 6fefc34ef602..7e087c344265 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1033,7 +1033,7 @@ static void ironlake_rps_change_irq_handler(struct drm_i915_private *dev_priv) static void notify_ring(struct intel_engine_cs *engine) { - smp_store_mb(engine->breadcrumbs.irq_posted, true); + set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted); if (intel_engine_wakeup(engine)) trace_i915_gem_request_notify(engine); } diff --git a/drivers/gpu/drm/i915/intel_breadcrumbs.c b/drivers/gpu/drm/i915/intel_breadcrumbs.c index c6fa77177615..3dea9e7e17e9 100644 --- a/drivers/gpu/drm/i915/intel_breadcrumbs.c +++ b/drivers/gpu/drm/i915/intel_breadcrumbs.c @@ -81,7 +81,7 @@ static void irq_enable(struct intel_engine_cs *engine) * we still need to force the barrier before reading the seqno, * just in case. */ - engine->breadcrumbs.irq_posted = true; + __set_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted); /* Caller disables interrupts */ spin_lock(&engine->i915->irq_lock); @@ -96,7 +96,7 @@ static void irq_disable(struct intel_engine_cs *engine) engine->irq_disable(engine); spin_unlock(&engine->i915->irq_lock); - engine->breadcrumbs.irq_posted = false; + __clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted); } static void __intel_breadcrumbs_enable_irq(struct intel_breadcrumbs *b) @@ -257,7 +257,8 @@ static bool __intel_engine_add_wait(struct intel_engine_cs *engine, * in case the seqno passed. */ __intel_breadcrumbs_enable_irq(b); - if (READ_ONCE(b->irq_posted)) + if (test_bit(ENGINE_IRQ_BREADCRUMB, + &engine->irq_posted)) wake_up_process(to_wait(next)->tsk); } @@ -610,7 +611,7 @@ void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine) if (intel_engine_has_waiter(engine)) { b->timeout = wait_timeout(); __intel_breadcrumbs_enable_irq(b); - if (READ_ONCE(b->irq_posted)) + if (test_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) wake_up_process(b->first_wait->tsk); } else { /* sanitize the IMR and unmask any auxiliary interrupts */ diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index dbd32585f27a..a9ea84ea3155 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -211,6 +211,9 @@ struct intel_engine_cs { struct intel_render_state *render_state; + unsigned long irq_posted; +#define ENGINE_IRQ_BREADCRUMB 0 + /* Rather than have every client wait upon all user interrupts, * with the herd waking after every interrupt and each doing the * heavyweight seqno dance, we delegate the task (of being the @@ -229,7 +232,6 @@ struct intel_engine_cs { */ struct intel_breadcrumbs { struct task_struct __rcu *irq_seqno_bh; /* bh for interrupts */ - bool irq_posted; spinlock_t lock; /* protects the lists of requests; irqsafe */ struct rb_root waiters; /* sorted by retirement, priority */