From patchwork Fri Feb 3 13:11:13 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 9554063 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D35CC602B7 for ; Fri, 3 Feb 2017 13:11:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C150827E33 for ; Fri, 3 Feb 2017 13:11:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B616F28173; Fri, 3 Feb 2017 13:11:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 662B627E33 for ; Fri, 3 Feb 2017 13:11:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8C25D6EB7A; Fri, 3 Feb 2017 13:11:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 261436EB7A for ; Fri, 3 Feb 2017 13:11:21 +0000 (UTC) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP; 03 Feb 2017 05:11:20 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.33,328,1477983600"; d="scan'208";a="55064203" Received: from linux.intel.com ([10.54.29.200]) by orsmga004.jf.intel.com with ESMTP; 03 Feb 2017 05:11:20 -0800 Received: from localhost (aconselv-mobl3.fi.intel.com [10.237.66.54]) by linux.intel.com (Postfix) with ESMTP id 38D2A6A4006; Fri, 3 Feb 2017 05:10:20 -0800 (PST) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Fri, 3 Feb 2017 15:11:13 +0200 Message-Id: <20170203131115.2058-2-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170203131115.2058-1-ander.conselvan.de.oliveira@intel.com> References: <20170203131115.2058-1-ander.conselvan.de.oliveira@intel.com> MIME-Version: 1.0 Cc: Ander Conselvan de Oliveira Subject: [Intel-gfx] [PATCH 1/3] drm/i915: Merge BDW pipe gamma and degamma table code X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The only difference between the code loading the pipe gamma and degamma tables in BDW is that the gamma code also writes the registers that hold the maximum values. So we can use the gamma code for the degamma table, at the expense of writing the maximum value register twice, with potenttially wrong values in the first time. v2: Pass PAL_PREC_SPLIT_MODE from the caller. (Ville) Cc: Ville Syrjälä Signed-off-by: Ander Conselvan de Oliveira --- drivers/gpu/drm/i915/intel_color.c | 59 ++++++++++---------------------------- 1 file changed, 15 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_color.c b/drivers/gpu/drm/i915/intel_color.c index 0627eee..82e1809 100644 --- a/drivers/gpu/drm/i915/intel_color.c +++ b/drivers/gpu/drm/i915/intel_color.c @@ -340,54 +340,20 @@ static void haswell_load_luts(struct drm_crtc_state *crtc_state) hsw_enable_ips(intel_crtc); } -static void bdw_load_degamma_lut(struct drm_crtc_state *state) +static void bdw_load_lut(struct drm_crtc_state *state, u32 offset, + struct drm_color_lut *lut, u32 lut_size, + u32 flags) { struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); enum pipe pipe = to_intel_crtc(state->crtc)->pipe; - uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size; - - I915_WRITE(PREC_PAL_INDEX(pipe), - PAL_PREC_SPLIT_MODE | PAL_PREC_AUTO_INCREMENT); - - if (state->degamma_lut) { - struct drm_color_lut *lut = - (struct drm_color_lut *) state->degamma_lut->data; - - for (i = 0; i < lut_size; i++) { - uint32_t word = - drm_color_lut_extract(lut[i].red, 10) << 20 | - drm_color_lut_extract(lut[i].green, 10) << 10 | - drm_color_lut_extract(lut[i].blue, 10); - - I915_WRITE(PREC_PAL_DATA(pipe), word); - } - } else { - for (i = 0; i < lut_size; i++) { - uint32_t v = (i * ((1 << 10) - 1)) / (lut_size - 1); - - I915_WRITE(PREC_PAL_DATA(pipe), - (v << 20) | (v << 10) | v); - } - } -} - -static void bdw_load_gamma_lut(struct drm_crtc_state *state, u32 offset) -{ - struct drm_i915_private *dev_priv = to_i915(state->crtc->dev); - enum pipe pipe = to_intel_crtc(state->crtc)->pipe; - uint32_t i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size; + uint32_t i; WARN_ON(offset & ~PAL_PREC_INDEX_VALUE_MASK); I915_WRITE(PREC_PAL_INDEX(pipe), - (offset ? PAL_PREC_SPLIT_MODE : 0) | - PAL_PREC_AUTO_INCREMENT | - offset); - - if (state->gamma_lut) { - struct drm_color_lut *lut = - (struct drm_color_lut *) state->gamma_lut->data; + flags | PAL_PREC_AUTO_INCREMENT | offset); + if (lut) { for (i = 0; i < lut_size; i++) { uint32_t word = (drm_color_lut_extract(lut[i].red, 10) << 20) | @@ -430,9 +396,13 @@ static void broadwell_load_luts(struct drm_crtc_state *state) return; } - bdw_load_degamma_lut(state); - bdw_load_gamma_lut(state, - INTEL_INFO(dev_priv)->color.degamma_lut_size); + bdw_load_lut(state, 0, (struct drm_color_lut *) state->degamma_lut, + INTEL_INFO(dev_priv)->color.degamma_lut_size, + PAL_PREC_SPLIT_MODE); + bdw_load_lut(state, INTEL_INFO(dev_priv)->color.degamma_lut_size, + (struct drm_color_lut *) state->gamma_lut, + INTEL_INFO(dev_priv)->color.gamma_lut_size, + PAL_PREC_SPLIT_MODE); intel_state->gamma_mode = GAMMA_MODE_MODE_SPLIT; I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_SPLIT); @@ -489,7 +459,8 @@ static void glk_load_luts(struct drm_crtc_state *state) } glk_load_degamma_lut(state); - bdw_load_gamma_lut(state, 0); + bdw_load_lut(state, 0, (struct drm_color_lut *) state->gamma_lut, + INTEL_INFO(dev_priv)->color.gamma_lut_size, 0); intel_state->gamma_mode = GAMMA_MODE_MODE_10BIT; I915_WRITE(GAMMA_MODE(pipe), GAMMA_MODE_MODE_10BIT);