From patchwork Fri Feb 17 16:38:33 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9580387 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 44C076042F for ; Fri, 17 Feb 2017 16:38:41 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2E67E28736 for ; Fri, 17 Feb 2017 16:38:41 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 205D528740; Fri, 17 Feb 2017 16:38:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9CE5028736 for ; Fri, 17 Feb 2017 16:38:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1604B6ED7A; Fri, 17 Feb 2017 16:38:40 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2BF3D6ED7B for ; Fri, 17 Feb 2017 16:38:38 +0000 (UTC) Received: by mail-wm0-x244.google.com with SMTP id r18so3470562wmd.3 for ; Fri, 17 Feb 2017 08:38:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=wnkhtLl0HT/mffGflwr2UTIGH2FUPh3NwFm3/WuSFUM=; b=P0uTZk5eXexFlMBb7sPhIZ/26tTUPsismfnIBw0CX2IvDuxvO7SAjyy+3XF5ux5QYx 2hBUKMLUgT8TW3cQSFWk2OuOZ8nHqTTObHZ9gncVEoqhH67IudLM3x66WcncaA70oPaP w5DD2/G97NNO2uxRLTM6ccmLQCi/tfOl+OrpRVJZJ3FHofy5SQ7HwtcuVMaDYt9EionE 9aF8Vl/LsGvp/u27Jgp3g/ATVHFF5BpxjGkvPflFSByE1N2OGJcP4yigthExIU45RYiX 4ke1H9+HfrGdr969f0bfr38stBbPIbEWRVd+tggr63xK47TpJ/PQCFhZgEUnCo0Vreek ihRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=wnkhtLl0HT/mffGflwr2UTIGH2FUPh3NwFm3/WuSFUM=; b=UC4DIqxgELB+ziDBVK6LDgo4j0tyoyjTXLmEY0qcDgti7Xl96EqbxN3sFfoY1Wcknq diWQeFBTwtQoON9/wupgEG41i/b8hag17mVTyqGqSNdHmVyajcT+fGq3wvJd+rO5otV8 mfj1iU53R+JH899JqRwM22F3CydV345YVzY+oIfVpzP4u+6ci5hr+nKD8l0jAfaU5ObL PMbEGoOA8NfY9nTpsV7sJcjEPi8rAwQa6qUPd5ltjDNZ7V0vA4B0Nro5revTgRcAWm+i wHoI9wWyAf0xtxRkXUJRi4r9AkwPdec9zSxUcY0rpS19GeWBCdwE5ASvyIyqnofjrV24 k5wg== X-Gm-Message-State: AMke39mXrIMDTw7zwQcGZACdCfS1LLemQFC4muOpjj6j7twD9xRDfL4Poo2WqTHzoKIj/w== X-Received: by 10.28.111.75 with SMTP id k72mr2704527wmc.39.1487349516851; Fri, 17 Feb 2017 08:38:36 -0800 (PST) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id m139sm2319066wma.2.2017.02.17.08.38.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 17 Feb 2017 08:38:36 -0800 (PST) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Fri, 17 Feb 2017 16:38:33 +0000 Message-Id: <20170217163833.731-1-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.11.0 Subject: [Intel-gfx] [PATCH] drm/i915: Assert that the request->tail is always qword aligned X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The hardware requires that the tail pointer only advance in qword units, so assert that the value we write is aligned to qwords, and similarly enforce this restriction onto the request->tail. Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Mika Kuoppala Reviewed-by: Michał Winiarski --- drivers/gpu/drm/i915/intel_lrc.c | 4 ++++ drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index afcb1f189162..d6b67be4715d 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -325,6 +325,7 @@ static u64 execlists_update_context(struct drm_i915_gem_request *rq) rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; u32 *reg_state = ce->lrc_reg_state; + GEM_BUG_ON(!IS_ALIGNED(rq->tail, 8)); reg_state[CTX_RING_TAIL+1] = rq->tail; /* True 32b PPGTT with dynamic page allocation: update PDP @@ -1283,6 +1284,7 @@ static void reset_common_ring(struct intel_engine_cs *engine, /* Reset WaIdleLiteRestore:bdw,skl as well */ request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32); + GEM_BUG_ON(!IS_ALIGNED(request->tail, 8)); } static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) @@ -1494,6 +1496,7 @@ static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs) *cs++ = MI_USER_INTERRUPT; *cs++ = MI_NOOP; request->tail = intel_ring_offset(request, cs); + GEM_BUG_ON(!IS_ALIGNED(request->tail, 8)); gen8_emit_wa_tail(request, cs); } @@ -1521,6 +1524,7 @@ static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request, *cs++ = MI_USER_INTERRUPT; *cs++ = MI_NOOP; request->tail = intel_ring_offset(request, cs); + GEM_BUG_ON(!IS_ALIGNED(request->tail, 8)); gen8_emit_wa_tail(request, cs); } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index d56f384938f7..f62afffef682 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -784,6 +784,7 @@ static void i9xx_submit_request(struct drm_i915_gem_request *request) i915_gem_request_submit(request); + GEM_BUG_ON(!IS_ALIGNED(request->tail, 8)); I915_WRITE_TAIL(request->engine, request->tail); } @@ -795,6 +796,7 @@ static void i9xx_emit_breadcrumb(struct drm_i915_gem_request *req, u32 *cs) *cs++ = MI_USER_INTERRUPT; req->tail = intel_ring_offset(req, cs); + GEM_BUG_ON(!IS_ALIGNED(req->tail, 8)); } static const int i9xx_emit_breadcrumb_sz = 4; @@ -833,6 +835,7 @@ static void gen8_render_emit_breadcrumb(struct drm_i915_gem_request *req, *cs++ = MI_NOOP; req->tail = intel_ring_offset(req, cs); + GEM_BUG_ON(!IS_ALIGNED(req->tail, 8)); } static const int gen8_render_emit_breadcrumb_sz = 8;