| Message ID | 20170220140845.1714-10-hdegoede@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, 20 Feb 2017 15:08:39 +0100 Hans de Goede <hdegoede@redhat.com> wrote: > Move the DPOunit clock gate workaround to directly after the PLL enable. > > The exact location of the workaround does not matter and there are 2 > reasons to group it with the PLL enable: > > 1) This moves it out of the middle of the init sequence from the spec, > making it easier to follow the init sequence / compare it to the spec > > 2) It is grouped with the pll disable call in intel_dsi_post_disable, > so for consistency it should be grouped with the pll enable in > intel_dsi_pre_enable > > Signed-off-by: Hans de Goede <hdegoede@redhat.com> Makes sense and looks better too. Reviewed-by: Bob Paauwe <bob.j.paauwe@intel.com> > --- > drivers/gpu/drm/i915/intel_dsi.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c > index de0558b..f4539f1 100644 > --- a/drivers/gpu/drm/i915/intel_dsi.c > +++ b/drivers/gpu/drm/i915/intel_dsi.c > @@ -649,14 +649,6 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, > I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0); > } > > - intel_dsi_prepare(encoder, pipe_config); > - > - /* Power on, try both CRC pmic gpio and VBT */ > - if (intel_dsi->gpio_panel) > - gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); > - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON); > - msleep(intel_dsi->panel_on_delay); > - > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { > u32 val; > > @@ -666,6 +658,14 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, > I915_WRITE(DSPCLK_GATE_D, val); > } > > + intel_dsi_prepare(encoder, pipe_config); > + > + /* Power on, try both CRC pmic gpio and VBT */ > + if (intel_dsi->gpio_panel) > + gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); > + intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON); > + msleep(intel_dsi->panel_on_delay); > + > /* put device in ready state */ > intel_dsi_device_ready(encoder); >
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c index de0558b..f4539f1 100644 --- a/drivers/gpu/drm/i915/intel_dsi.c +++ b/drivers/gpu/drm/i915/intel_dsi.c @@ -649,14 +649,6 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, I915_WRITE(BXT_P_DSI_REGULATOR_TX_CTRL, 0); } - intel_dsi_prepare(encoder, pipe_config); - - /* Power on, try both CRC pmic gpio and VBT */ - if (intel_dsi->gpio_panel) - gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); - intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON); - msleep(intel_dsi->panel_on_delay); - if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { u32 val; @@ -666,6 +658,14 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder, I915_WRITE(DSPCLK_GATE_D, val); } + intel_dsi_prepare(encoder, pipe_config); + + /* Power on, try both CRC pmic gpio and VBT */ + if (intel_dsi->gpio_panel) + gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); + intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON); + msleep(intel_dsi->panel_on_delay); + /* put device in ready state */ intel_dsi_device_ready(encoder);
Move the DPOunit clock gate workaround to directly after the PLL enable. The exact location of the workaround does not matter and there are 2 reasons to group it with the PLL enable: 1) This moves it out of the middle of the init sequence from the spec, making it easier to follow the init sequence / compare it to the spec 2) It is grouped with the pll disable call in intel_dsi_post_disable, so for consistency it should be grouped with the pll enable in intel_dsi_pre_enable Signed-off-by: Hans de Goede <hdegoede@redhat.com> --- drivers/gpu/drm/i915/intel_dsi.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)