From patchwork Thu Mar 9 10:22:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9612967 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D544B604D9 for ; Thu, 9 Mar 2017 10:22:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C39AC285D4 for ; Thu, 9 Mar 2017 10:22:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B6F1F285E0; Thu, 9 Mar 2017 10:22:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9DCC2285D4 for ; Thu, 9 Mar 2017 10:22:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4BFD86EBBB; Thu, 9 Mar 2017 10:22:31 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id 765976EBBB for ; Thu, 9 Mar 2017 10:22:29 +0000 (UTC) Received: by mail-wm0-x241.google.com with SMTP id u132so10137127wmg.1 for ; Thu, 09 Mar 2017 02:22:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=xXYpMhndj4H/67LKRdYDyLqGO5yv6Fzfk7UGC38sEb4=; b=Zn99Ol90Xz5ahgzON/ghRoc4dgQ2gc+/GFxNZYxdTeSTnCVlSW+ExVX6maGbze53qC jzFLoe16zlpXHCW0k6UJX/W0UVPX2g+slipx6lhAIaF5dK5T3IFja/ZXP02aPAYe1Jlb Qd4P3j3fiIGdEOIxxan+Fel6Sl3OdKWK1UBu9v3hmhiI5aaRHMLGU5dPfWVBE56+HZBW QlTw2LWDO2BrG806t5OGfKX85SlxwKqQhyKuNt9B2UIwt0RTVtOgOA2DMBfP7DojWPv+ nYLtO88nte2HPyk2ohqo9sQWo1fJ6Go/OnFOlXud4pBK6AYAz+GNk1BazTzXrfe5pyCx oQAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=xXYpMhndj4H/67LKRdYDyLqGO5yv6Fzfk7UGC38sEb4=; b=ugfZvPqJTo9Kg/jhlPay3/QIvtQPkCg9OXjwE2rT+fJT9NCm95WcmGk7CXdX5xRLif xmTVcT2QsoDAR/oj0MpdiFJoQqQOwLicJtVfE7qEwbiyFeqLcXQ2CDlVKtPwN0BStK1u ta9qcPmVGXEF7nIiBj4usNaw7zOYbphNDJpeLG/89hU3ACFNbVuviW6qf+Y0TyJul/LK DkB7+MLXknu7XoOOAX/QBXLBz2sNHbGOLMqWseTKE7DG45Pagr2CD2xPt1Eojau+Y+KX +SuzDJ+9Va9Xlw0zHkriscNMaCLQQ+fZyOcuegFor1dKTKi4z9gNp9WngKEMxOrPK+pr CWLQ== X-Gm-Message-State: AMke39koXdMqsAjcgAgipxbQL+svvCDkxqEDoo6eHjbtEGs+9FKdHtSg6pJQE5iTaTHLqg== X-Received: by 10.28.19.207 with SMTP id 198mr9168891wmt.49.1489054948097; Thu, 09 Mar 2017 02:22:28 -0800 (PST) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id j34sm7622944wre.7.2017.03.09.02.22.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 09 Mar 2017 02:22:27 -0800 (PST) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Thu, 9 Mar 2017 10:22:25 +0000 Message-Id: <20170309102225.25330-1-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.11.0 Cc: Mika Kuoppala Subject: [Intel-gfx] [PATCH] drm/i915: Restore engine->submit_request before unwedging X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP When we wedge the device, we override engine->submit_request with a nop to ensure that all in-flight requests are marked in error. However, igt would like to unwedge the device to test -EIO handling. This requires us to flush those in-flight requests and restore the original engine->submit_request. Fixes: 821ed7df6e2a ("drm/i915: Update reset path to fix incomplete requests") Testcase: igt/gem_eio Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Mika Kuoppala --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 41 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_ringbuffer.c | 12 ++++++++++ drivers/gpu/drm/i915/intel_ringbuffer.h | 2 ++ 5 files changed, 57 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index b1e9027a4f80..576b03b0048c 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1825,7 +1825,7 @@ void i915_reset(struct drm_i915_private *dev_priv) return; /* Clear any previous failed attempts at recovery. Time to try again. */ - __clear_bit(I915_WEDGED, &error->flags); + i915_gem_unset_wedged(dev_priv); error->reset_count++; pr_notice("drm/i915: Resetting chip after gpu hang\n"); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3002996ddbed..c52aee5141ca 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -3409,6 +3409,7 @@ int i915_gem_reset_prepare(struct drm_i915_private *dev_priv); void i915_gem_reset(struct drm_i915_private *dev_priv); void i915_gem_reset_finish(struct drm_i915_private *dev_priv); void i915_gem_set_wedged(struct drm_i915_private *dev_priv); +void i915_gem_unset_wedged(struct drm_i915_private *dev_priv); void i915_gem_init_mmio(struct drm_i915_private *i915); int __must_check i915_gem_init(struct drm_i915_private *dev_priv); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index aca1eaddafb4..0725e7a591a5 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -2999,6 +2999,47 @@ void i915_gem_set_wedged(struct drm_i915_private *dev_priv) mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); } +void i915_gem_unset_wedged(struct drm_i915_private *dev_priv) +{ + struct i915_gem_timeline *tl; + int i; + + lockdep_assert_held(&dev_priv->drm.struct_mutex); + if (!test_bit(I915_WEDGED, &dev_priv->gpu_error.flags)) + return; + + /* Before unwedging, make sure that all pending operations + * are flushed and errored out. No more can be submitted until + * we reset the wedged bit. + */ + list_for_each_entry(tl, &dev_priv->gt.timelines, link) { + for (i = 0; i < ARRAY_SIZE(tl->engine); i++) { + struct drm_i915_gem_request *rq; + + rq = i915_gem_active_peek(&tl->engine[i].last_request, + &dev_priv->drm.struct_mutex); + if (!rq) + continue; + + /* We can't use our normal waiter as we want to + * avoid recursively trying to handle the current + * reset. + */ + dma_fence_default_wait(&rq->fence, false, + MAX_SCHEDULE_TIMEOUT); + } + } + + /* Undo nop_submit_request */ + if (i915.enable_execlists) + intel_execlists_enable_submission(dev_priv); + else + intel_ringbuffer_enable_submission(dev_priv); + + smp_mb__before_atomic(); + clear_bit(I915_WEDGED, &dev_priv->gpu_error.flags); +} + static void i915_gem_retire_work_handler(struct work_struct *work) { diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 4a864f8c9387..753586f6ddbe 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -2224,3 +2224,15 @@ int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) return intel_init_ring_buffer(engine); } + +void intel_ringbuffer_enable_submission(struct drm_i915_private *i915) +{ + struct intel_engine_cs *engine; + enum intel_engine_id id; + + for_each_engine(engine, i915, id) { + engine->submit_request = i9xx_submit_request; + if (IS_GEN6(i915) && id == VCS) + engine->submit_request = gen6_bsd_submit_request; + } +} diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 0ef491df5b4e..5601c24b266a 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -669,4 +669,6 @@ static inline u32 *gen8_emit_pipe_control(u32 *batch, u32 flags, u32 offset) bool intel_engine_is_idle(struct intel_engine_cs *engine); bool intel_engines_are_idle(struct drm_i915_private *dev_priv); +void intel_ringbuffer_enable_submission(struct drm_i915_private *i915); + #endif /* _INTEL_RINGBUFFER_H_ */