From patchwork Fri Mar 17 14:04:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ander Conselvan de Oliveira X-Patchwork-Id: 9630791 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id A8C7B60132 for ; Fri, 17 Mar 2017 14:05:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9063228533 for ; Fri, 17 Mar 2017 14:05:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8524728543; Fri, 17 Mar 2017 14:05:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1300F28533 for ; Fri, 17 Mar 2017 14:05:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C24586E0F8; Fri, 17 Mar 2017 14:05:01 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 96F176E0F8 for ; Fri, 17 Mar 2017 14:05:00 +0000 (UTC) Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP; 17 Mar 2017 07:05:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.36,176,1486454400"; d="scan'208";a="945450811" Received: from linux.intel.com ([10.54.29.200]) by orsmga003.jf.intel.com with ESMTP; 17 Mar 2017 07:05:00 -0700 Received: from localhost (aconselv-mobl3.fi.intel.com [10.237.66.54]) by linux.intel.com (Postfix) with ESMTP id 145162C8001; Fri, 17 Mar 2017 07:04:54 -0700 (PDT) From: Ander Conselvan de Oliveira To: intel-gfx@lists.freedesktop.org Date: Fri, 17 Mar 2017 16:04:36 +0200 Message-Id: <20170317140436.24645-1-ander.conselvan.de.oliveira@intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <87tw6syznm.fsf@gaia.fi.intel.com> References: <87tw6syznm.fsf@gaia.fi.intel.com> Cc: Ander Conselvan de Oliveira , Mika Kuoppala , Arun Siluvery Subject: [Intel-gfx] [PATCH v2] drm/i915/glk: Enable pooled EUs for Geminilake X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Geminilake also supports pooled EUs. Enable it. It is unclear if the recommendation to disable it for 2x6 configurations from commit e015dd69b2cf ("drm/i915/bxt: Add WaEnablePooledEuFor2x6") should also apply to GLK, but it is applied anyway to be on the safe side. That restriction can be lifted later if determined not to impact performance. The extra restriction should not impact user space either. The only user space that uses this feature is Beignet, and it only does so for 3x6 devices. See See Beignet's commit 6901899ec90a ("Runtime: set the sub slice according to kernel pooled EU configure."). v2: Improve commit message. (Mika, Roy) Cc: Arun Siluvery Cc: Mika Kuoppala Cc: Tvrtko Ursulin Cc: Yang Rong Signed-off-by: Ander Conselvan de Oliveira Reviewed-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_device_info.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 9fc6ab7..7d01dfe 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -197,8 +197,10 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1; sseu->has_eu_pg = sseu->eu_per_subslice > 2; - if (IS_BROXTON(dev_priv)) { + if (IS_GEN9_LP(dev_priv)) { #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask & BIT(ss))) + info->has_pooled_eu = hweight8(sseu->subslice_mask) == 3; + /* * There is a HW issue in 2x6 fused down parts that requires * Pooled EU to be enabled as a WA. The pool configuration @@ -206,9 +208,8 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) * doesn't affect if the device has all 3 subslices enabled. */ /* WaEnablePooledEuFor2x6:bxt */ - info->has_pooled_eu = ((hweight8(sseu->subslice_mask) == 3) || - (hweight8(sseu->subslice_mask) == 2 && - INTEL_REVID(dev_priv) < BXT_REVID_C0)); + info->has_pooled_eu |= (hweight8(sseu->subslice_mask) == 2 && + IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST)); sseu->min_eu_in_pool = 0; if (info->has_pooled_eu) {