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[10/14] drm/i915: Eliminate ironlake_update_primary_plane()

Message ID 20170317211808.14693-11-ville.syrjala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Ville Syrjälä March 17, 2017, 9:18 p.m. UTC 
From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The effective difference between i9xx_update_primary_plane()
and ironlake_update_primary_plane() is only the HSW/BDW
DSPOFFSET special case. So bring that over into
i9xx_update_primary_plane() and eliminate the duplicated code.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 55 ++++--------------------------------
 1 file changed, 6 insertions(+), 49 deletions(-)

Comments

Chris Wilson March 17, 2017, 10:06 p.m. UTC | #1 
On Fri, Mar 17, 2017 at 11:18:04PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The effective difference between i9xx_update_primary_plane()
> and ironlake_update_primary_plane() is only the HSW/BDW
> DSPOFFSET special case. So bring that over into
> i9xx_update_primary_plane() and eliminate the duplicated code.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 55 ++++--------------------------------
>  1 file changed, 6 insertions(+), 49 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 024614cb47b6..c7f6bc4e605a 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3109,7 +3109,12 @@ static void i9xx_update_primary_plane(struct drm_plane *primary,
>  	I915_WRITE_FW(reg, dspcntr);
>  
>  	I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
> -	if (INTEL_GEN(dev_priv) >= 4) {
> +	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> +		I915_WRITE_FW(DSPSURF(plane),
> +			      intel_plane_ggtt_offset(plane_state) +
> +			      intel_crtc->dspaddr_offset);
> +		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
> +	} else if (INTEL_GEN(dev_priv) >= 4) {
>  		I915_WRITE_FW(DSPSURF(plane),
>  			      intel_plane_ggtt_offset(plane_state) +
>  			      intel_crtc->dspaddr_offset);
> @@ -3146,48 +3151,6 @@ static void i9xx_disable_primary_plane(struct drm_plane *primary,
>  	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
>  }
>  
> -static void ironlake_update_primary_plane(struct drm_plane *primary,
> -					  const struct intel_crtc_state *crtc_state,
> -					  const struct intel_plane_state *plane_state)
> -{
> -	struct drm_device *dev = primary->dev;
> -	struct drm_i915_private *dev_priv = to_i915(dev);
> -	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
> -	struct drm_framebuffer *fb = plane_state->base.fb;
> -	int plane = intel_crtc->plane;
> -	u32 linear_offset;
> -	u32 dspcntr = plane_state->ctl;
> -	i915_reg_t reg = DSPCNTR(plane);
> -	int x = plane_state->main.x;
> -	int y = plane_state->main.y;
> -	unsigned long irqflags;
> -
> -	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
> -
> -	intel_crtc->dspaddr_offset = plane_state->main.offset;
> -
> -	intel_crtc->adjusted_x = x;
> -	intel_crtc->adjusted_y = y;
> -
> -	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
> -
> -	I915_WRITE_FW(reg, dspcntr);
> -
> -	I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
> -	I915_WRITE_FW(DSPSURF(plane),
> -		      intel_plane_ggtt_offset(plane_state) +
> -		      intel_crtc->dspaddr_offset);
> -	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> -		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
> -	} else {
> -		I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
> -		I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
> -	}
> -	POSTING_READ_FW(reg);
> -
> -	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
> -}
> -
>  static u32
>  intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
>  {
> @@ -13642,12 +13605,6 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
>  
>  		primary->update_plane = skylake_update_primary_plane;
>  		primary->disable_plane = skylake_disable_primary_plane;
> -	} else if (HAS_PCH_SPLIT(dev_priv)) {
> -		intel_primary_formats = i965_primary_formats;
> -		num_formats = ARRAY_SIZE(i965_primary_formats);
> -
> -		primary->update_plane = ironlake_update_primary_plane;
> -		primary->disable_plane = i9xx_disable_primary_plane;
>  	} else if (INTEL_GEN(dev_priv) >= 4) {

Oh, that looks quite odd, but it checks out.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 024614cb47b6..c7f6bc4e605a 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3109,7 +3109,12 @@  static void i9xx_update_primary_plane(struct drm_plane *primary,
 	I915_WRITE_FW(reg, dspcntr);
 
 	I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
-	if (INTEL_GEN(dev_priv) >= 4) {
+	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
+		I915_WRITE_FW(DSPSURF(plane),
+			      intel_plane_ggtt_offset(plane_state) +
+			      intel_crtc->dspaddr_offset);
+		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
+	} else if (INTEL_GEN(dev_priv) >= 4) {
 		I915_WRITE_FW(DSPSURF(plane),
 			      intel_plane_ggtt_offset(plane_state) +
 			      intel_crtc->dspaddr_offset);
@@ -3146,48 +3151,6 @@  static void i9xx_disable_primary_plane(struct drm_plane *primary,
 	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
 }
 
-static void ironlake_update_primary_plane(struct drm_plane *primary,
-					  const struct intel_crtc_state *crtc_state,
-					  const struct intel_plane_state *plane_state)
-{
-	struct drm_device *dev = primary->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
-	struct drm_framebuffer *fb = plane_state->base.fb;
-	int plane = intel_crtc->plane;
-	u32 linear_offset;
-	u32 dspcntr = plane_state->ctl;
-	i915_reg_t reg = DSPCNTR(plane);
-	int x = plane_state->main.x;
-	int y = plane_state->main.y;
-	unsigned long irqflags;
-
-	linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
-
-	intel_crtc->dspaddr_offset = plane_state->main.offset;
-
-	intel_crtc->adjusted_x = x;
-	intel_crtc->adjusted_y = y;
-
-	spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
-
-	I915_WRITE_FW(reg, dspcntr);
-
-	I915_WRITE_FW(DSPSTRIDE(plane), fb->pitches[0]);
-	I915_WRITE_FW(DSPSURF(plane),
-		      intel_plane_ggtt_offset(plane_state) +
-		      intel_crtc->dspaddr_offset);
-	if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
-		I915_WRITE_FW(DSPOFFSET(plane), (y << 16) | x);
-	} else {
-		I915_WRITE_FW(DSPTILEOFF(plane), (y << 16) | x);
-		I915_WRITE_FW(DSPLINOFF(plane), linear_offset);
-	}
-	POSTING_READ_FW(reg);
-
-	spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
-}
-
 static u32
 intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
 {
@@ -13642,12 +13605,6 @@  intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 
 		primary->update_plane = skylake_update_primary_plane;
 		primary->disable_plane = skylake_disable_primary_plane;
-	} else if (HAS_PCH_SPLIT(dev_priv)) {
-		intel_primary_formats = i965_primary_formats;
-		num_formats = ARRAY_SIZE(i965_primary_formats);
-
-		primary->update_plane = ironlake_update_primary_plane;
-		primary->disable_plane = i9xx_disable_primary_plane;
 	} else if (INTEL_GEN(dev_priv) >= 4) {
 		intel_primary_formats = i965_primary_formats;
 		num_formats = ARRAY_SIZE(i965_primary_formats);