From patchwork Sat Mar 25 20:10:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9644831 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1D96960327 for ; Sat, 25 Mar 2017 20:11:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 050F726220 for ; Sat, 25 Mar 2017 20:11:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EA08527FAE; Sat, 25 Mar 2017 20:10:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6B5CC26220 for ; Sat, 25 Mar 2017 20:10:59 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E2746E0D0; Sat, 25 Mar 2017 20:10:58 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wr0-x244.google.com (mail-wr0-x244.google.com [IPv6:2a00:1450:400c:c0c::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 41EFE6E0D0 for ; Sat, 25 Mar 2017 20:10:57 +0000 (UTC) Received: by mail-wr0-x244.google.com with SMTP id u1so3048340wra.3 for ; Sat, 25 Mar 2017 13:10:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=jeazEUq5nkVZl4cL1nDP62Wep9eDIEJjJA9ulPSAmAc=; b=ISq6udRG3RnKhHYMinlAWwwhZ8iUlKWGafmQH+Fx+o0+sIGSBP1jLKU66C+VxgXsgM 6qRNgcpSqhhOpbMTwA03WqEKiw3ywUaS3AolgVorxEw2BBmFjimpDPv5cuGAxMpT+W9v s1wGr55UYfUsrEImuJHHxezlToC+QzZS4sYMp5MSuVmpjEMxhTZTT2B0AQKMs3md6RVm DeNNLhpzN/5J9gwTbEG69uQ73Okj1OhM4Vn3jR5E6h2q8MKjzT3RrTdDZ5T05TEqC7oe XATJjxidrYghUZSGCo2ZO13cTrf2sEQcyBRUWqF5SsmUhaZbSMiPFfVptt3isNDn9Uls Tnyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=jeazEUq5nkVZl4cL1nDP62Wep9eDIEJjJA9ulPSAmAc=; b=GWnr7FW2RS4T7ydtnNY6QYEK0t0VM/y2jl5bxBh4rOVxBmt/Jd/mYct373m/lkzvy1 sMLGXGxhGW8PB4g3jr+JEaJ6ztswrwFneGJ+6mZvwVTZiuEfaEP5hnvQlnTnzp5ZcTvh y/uuFoI6UinDnsElnNmH9wBDSXECVied9eZVrxnActVZQ+OzzTgNbK5RyFBATCUj/GL2 fkOCZGaE17DB/FEYCMYtHZhVXJATwQb15NOROewngcr0ZHzoCOBQ/9W3+/8cT+QBtTkS xDISNp/NdsL4NEWo/F7pG3IXYKoqIXB9Kf2XhgoFe7bmMGI51BHDKw1aVxB5cqtCEdbD mqvA== X-Gm-Message-State: AFeK/H0iQUPC4gGZ3ybGSEm41UDEVZApjQ7AOnIhPpN7CNW7SCH2xwYW/QC8GCF5kc8s8g== X-Received: by 10.223.147.98 with SMTP id 89mr7112762wro.99.1490472655680; Sat, 25 Mar 2017 13:10:55 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id w12sm8175578wra.21.2017.03.25.13.10.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 25 Mar 2017 13:10:55 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Sat, 25 Mar 2017 20:10:53 +0000 Message-Id: <20170325201053.21306-1-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.11.0 Subject: [Intel-gfx] [PATCH] drm/i915/execlists: Trim irq handler X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP I noticed that gcc was spilling the CSB to the stack, so rearrange the code to be more compact. Spilling in this function is slightly more interesting due to the mmio reads acting as memory barriers and so end up flushing the stack spills. Still miniscule to having to do at least the pair of uncached reads :( function old new delta intel_lrc_irq_handler 1039 878 -161 Signed-off-by: Chris Wilson Cc: Tvrtko Ursulin Cc: Mika Kuoppala Reviewed-by: Tvrtko Ursulin --- drivers/gpu/drm/i915/intel_lrc.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index d45e6d13545a..e9822b0b308d 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -506,7 +506,7 @@ static void intel_lrc_irq_handler(unsigned long data) dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); u32 __iomem *buf = dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)); - unsigned int csb, head, tail; + unsigned int head, tail; /* The write will be ordered by the uncached read (itself * a memory barrier), so we do not need another in the form @@ -519,17 +519,14 @@ static void intel_lrc_irq_handler(unsigned long data) * is set and we do a new loop. */ __clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); - csb = readl(csb_mmio); - head = GEN8_CSB_READ_PTR(csb); - tail = GEN8_CSB_WRITE_PTR(csb); - if (head == tail) - break; + head = readl(csb_mmio); + tail = GEN8_CSB_WRITE_PTR(head); + head = GEN8_CSB_READ_PTR(head); + while (head != tail) { + unsigned int status; - if (tail < head) - tail += GEN8_CSB_ENTRIES; - do { - unsigned int idx = ++head % GEN8_CSB_ENTRIES; - unsigned int status = readl(buf + 2 * idx); + if (++head == GEN8_CSB_ENTRIES) + head = 0; /* We are flying near dragons again. * @@ -548,11 +545,12 @@ static void intel_lrc_irq_handler(unsigned long data) * status notifier. */ + status = readl(buf + 2 * head); if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) continue; /* Check the context/desc id for this event matches */ - GEM_DEBUG_BUG_ON(readl(buf + 2 * idx + 1) != + GEM_DEBUG_BUG_ON(readl(buf + 2 * head + 1) != port[0].context_id); GEM_BUG_ON(port[0].count == 0); @@ -570,10 +568,9 @@ static void intel_lrc_irq_handler(unsigned long data) GEM_BUG_ON(port[0].count == 0 && !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); - } while (head < tail); + } - writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, - GEN8_CSB_WRITE_PTR(csb) << 8), + writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8), csb_mmio); }