From patchwork Wed Apr 12 12:48:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 9677461 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F2BD460325 for ; Wed, 12 Apr 2017 12:48:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E4507285FE for ; Wed, 12 Apr 2017 12:48:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D91EE2866A; Wed, 12 Apr 2017 12:48:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 60CC3285FE for ; Wed, 12 Apr 2017 12:48:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 098C36E6E6; Wed, 12 Apr 2017 12:48:32 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x244.google.com (mail-wm0-x244.google.com [IPv6:2a00:1450:400c:c09::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id B34956E6E7 for ; Wed, 12 Apr 2017 12:48:29 +0000 (UTC) Received: by mail-wm0-x244.google.com with SMTP id d79so6221261wmi.2 for ; Wed, 12 Apr 2017 05:48:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id; bh=GuN7a955TmGzaGSVTeS3cDGDO0DRpANCS+iU6R12y9Y=; b=ew9CRadQ0BvX1jMFZjhiAnVPB/zC72Am15AJ1aAG9r7f2f+Annn4wRx7DwTJY365SP OrJT46Z4yIYuK2sxhtZlrL3rA+bSuK768+Je/Cfs9yZ3PgI2xzFs5L9t5L+AL36Ic2rO 1/Ct1uc27fcCfO7rXDGQlPTg3dQavD8iHaQdW75Cl5OLwglTXtMZSsx7hiABCkD/Lz6M oXVxbo5GOUcx0LN9wUUW0rgKNnjs+nvI+8hqNz4vEv04mM60rmTUpCHALSRWmxKREEaT 2SxjK0NSatp24MkvMgO/DaKn4ZJQzvC+2mzdCg/Cpc2rUSu/YvUr0yybSQhv02+FD1Bu nolg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id; bh=GuN7a955TmGzaGSVTeS3cDGDO0DRpANCS+iU6R12y9Y=; b=XEqTEvhQVqRnFvPd3o1vN77ogGi70WrE301ILM7cg0U2LYcm57yiXSifU93F668xhF /L0dp3pEH+9S//q4CffhG5i6CNfGYk7rselw8xyiNkvaeJ+uYB5k7QGyOlcRwGjzqP8Z DsMOBdxtgiPuOnQWsVgKldznoytc94dFNkjM6WjZDclfkKWwsH5W+HUXm1YcsoX7akrj BmmrinWdeLXg2YeXBaiVQStZGFZ4VD7OqqMVQVMY6tegtHqDwnIBb1ChIeYGKtQBsRS9 uPh4KarE3mMfEDwLCUeURUDsHFiHwMESpS8p92zthtG8zIz6bDnyKmTmK3aF39ZX6ZaQ IFZw== X-Gm-Message-State: AN3rC/5At13CuosZUVocP1/zdtVZUhd6jDeiHtHgQvtYaKZoOKHKcI4OSXMcRgODsL5WWQ== X-Received: by 10.28.91.82 with SMTP id p79mr2628261wmb.130.1492001308397; Wed, 12 Apr 2017 05:48:28 -0700 (PDT) Received: from haswell.alporthouse.com ([78.156.65.138]) by smtp.gmail.com with ESMTPSA id a10sm25621345wra.17.2017.04.12.05.48.27 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 12 Apr 2017 05:48:27 -0700 (PDT) From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Wed, 12 Apr 2017 13:48:17 +0100 Message-Id: <20170412124825.21741-1-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.11.0 Cc: Daniel Vetter Subject: [Intel-gfx] [PATCH v2 1/9] drm/i915: Mark up clflushes as belonging to an unordered timeline X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP 2 clflushes on two different objects are not ordered, and so do not belong to the same timeline (context). Either we use a unique context for each, or we reserve a special global context to mean unordered. Ideally, we would reserve 0 to mean unordered (DMA_FENCE_NO_CONTEXT) to have the same semantics everywhere. Signed-off-by: Chris Wilson Cc: Daniel Vetter Cc: Joonas Lahtinen Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_gem_clflush.c | 8 +------- drivers/gpu/drm/i915/i915_gem_clflush.h | 1 - 4 files changed, 4 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1af4e6f5410c..9ff399fdf92b 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1511,6 +1511,8 @@ struct i915_gem_mm { /** LRU list of objects with fence regs on them. */ struct list_head fence_list; + u64 unordered_timeline; + /* the indicator for dispatch video commands on two BSD rings */ atomic_t bsd_engine_dispatch_index; diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 33fb11cc5acc..68c0a1c3bf77 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4746,7 +4746,7 @@ int i915_gem_init(struct drm_i915_private *dev_priv) mutex_lock(&dev_priv->drm.struct_mutex); - i915_gem_clflush_init(dev_priv); + dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1); if (!i915.enable_execlists) { dev_priv->gt.resume = intel_legacy_submission_resume; diff --git a/drivers/gpu/drm/i915/i915_gem_clflush.c b/drivers/gpu/drm/i915/i915_gem_clflush.c index ffd01e02fe94..ffac7a1f0caf 100644 --- a/drivers/gpu/drm/i915/i915_gem_clflush.c +++ b/drivers/gpu/drm/i915/i915_gem_clflush.c @@ -27,7 +27,6 @@ #include "i915_gem_clflush.h" static DEFINE_SPINLOCK(clflush_lock); -static u64 clflush_context; struct clflush { struct dma_fence dma; /* Must be first for dma_fence_free() */ @@ -157,7 +156,7 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj, dma_fence_init(&clflush->dma, &i915_clflush_ops, &clflush_lock, - clflush_context, + to_i915(obj->base.dev)->mm.unordered_timeline, 0); i915_sw_fence_init(&clflush->wait, i915_clflush_notify); @@ -182,8 +181,3 @@ void i915_gem_clflush_object(struct drm_i915_gem_object *obj, GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU); } } - -void i915_gem_clflush_init(struct drm_i915_private *i915) -{ - clflush_context = dma_fence_context_alloc(1); -} diff --git a/drivers/gpu/drm/i915/i915_gem_clflush.h b/drivers/gpu/drm/i915/i915_gem_clflush.h index b62d61a2d15f..2455a7820937 100644 --- a/drivers/gpu/drm/i915/i915_gem_clflush.h +++ b/drivers/gpu/drm/i915/i915_gem_clflush.h @@ -28,7 +28,6 @@ struct drm_i915_private; struct drm_i915_gem_object; -void i915_gem_clflush_init(struct drm_i915_private *i915); void i915_gem_clflush_object(struct drm_i915_gem_object *obj, unsigned int flags); #define I915_CLFLUSH_FORCE BIT(0)