From patchwork Thu Apr 20 21:56:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthias Kaehlcke X-Patchwork-Id: 9691387 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 225E76037F for ; Thu, 20 Apr 2017 21:56:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 082241FF3D for ; Thu, 20 Apr 2017 21:56:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EEBE728497; Thu, 20 Apr 2017 21:56:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.7 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 5E2821FF3D for ; Thu, 20 Apr 2017 21:56:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2D8F06E327; Thu, 20 Apr 2017 21:56:33 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-oi0-f42.google.com (mail-oi0-f42.google.com [209.85.218.42]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3B5C26E327 for ; Thu, 20 Apr 2017 21:56:32 +0000 (UTC) Received: by mail-oi0-f42.google.com with SMTP id r203so69326364oib.3 for ; Thu, 20 Apr 2017 14:56:32 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=+xhT5TEQtMSmtWUNIl8vqioPcEdZ0qAX+Nu3VaaHxxc=; b=dCFi3rjae5jvsnWKJo3Z+boSymR/4aoHJ3j7FtfD3JKmoLlZa1XZ4rFDk3ykd6vtrB UyLbASl1DfCyJTog/dTZT28+iM2+22QnFAO/ZKlg1jrwoTFqipn0dx3cTm3IZkiqq4CY PqV4TKBn4Bvb8kzrsf1uHjqwyGaVedbkSVV2eF0QvZkrF5jMk2kpwIu1RfqT/fBtZ3It cvYw27h5rS5RhcIVHuKdUe28mczaURw3vKncZZBFmfmmAzKO6yj/hZhjRfVBJC3/GgKQ NrPyhSIyhTpTd07yl98vxOXRlzZTqk5DhYT2/AqYu08bFrsLckZIZUjVFcNCO8Ns4UYZ E64w== X-Gm-Message-State: AN3rC/6zuTdbnu+XS7YFqb5tfMHRCrOAuhagYWNNnY17Y+LNMxD43jmZ Zul2F4buBSAaAC7f X-Received: by 10.84.171.129 with SMTP id l1mr12429486plb.5.1492725391221; Thu, 20 Apr 2017 14:56:31 -0700 (PDT) Received: from mka.mtv.corp.google.com ([172.22.64.162]) by smtp.gmail.com with ESMTPSA id w129sm12114217pfb.130.2017.04.20.14.56.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 20 Apr 2017 14:56:30 -0700 (PDT) From: Matthias Kaehlcke To: Daniel Vetter , Jani Nikula , David Airlie Date: Thu, 20 Apr 2017 14:56:05 -0700 Message-Id: <20170420215605.176722-1-mka@chromium.org> X-Mailer: git-send-email 2.12.2.816.g2cccc81164-goog Cc: Grant Grundler , intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Greg Hackmann , Michael Davidson , Matthias Kaehlcke , dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH RESEND] drm/i915: Fix pipe/transcoder enum mismatches X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP In several instances the driver passes an 'enum pipe' value to a function expecting an 'enum transcoder' and viceversa. Since PIPE_x and TRANSCODER_x have the same values this doesn't cause functional problems. Still it is incorrect and causes clang to generate warnings like this: drivers/gpu/drm/i915/intel_display.c:1844:34: warning: implicit conversion from enumeration type 'enum transcoder' to different enumeration type 'enum pipe' [-Wenum-conversion] assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); Change the code to pass values of the type expected by the callee. Signed-off-by: Matthias Kaehlcke --- drivers/gpu/drm/i915/intel_display.c | 4 ++-- drivers/gpu/drm/i915/intel_dp.c | 6 ++++-- drivers/gpu/drm/i915/intel_hdmi.c | 6 ++++-- drivers/gpu/drm/i915/intel_sdvo.c | 6 ++++-- 4 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index ed1f4f272b4f..23484f042fae 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -1841,7 +1841,7 @@ static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, /* FDI must be feeding us bits for PCH ports */ assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); - assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); + assert_fdi_rx_enabled(dev_priv, PIPE_A); /* Workaround: set timing override bit. */ val = I915_READ(TRANS_CHICKEN2(PIPE_A)); @@ -4607,7 +4607,7 @@ static void lpt_pch_enable(struct drm_crtc *crtc) struct intel_crtc *intel_crtc = to_intel_crtc(crtc); enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; - assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); + assert_pch_transcoder_disabled(dev_priv, PIPE_A); lpt_program_iclkip(crtc); diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index d1670b8afbf5..454c2d3dfdd6 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -3568,7 +3568,8 @@ intel_dp_link_down(struct intel_dp *intel_dp) * doing the workaround. Sweep them under the rug. */ intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); + intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, + false); /* always enable with pattern 1 (as per spec) */ DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK); @@ -3582,7 +3583,8 @@ intel_dp_link_down(struct intel_dp *intel_dp) intel_wait_for_vblank_if_active(dev_priv, PIPE_A); intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); + intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, + true); } msleep(intel_dp->panel_power_down_delay); diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c index 24b2fa5b6282..48b1f5d37204 100644 --- a/drivers/gpu/drm/i915/intel_hdmi.c +++ b/drivers/gpu/drm/i915/intel_hdmi.c @@ -1153,7 +1153,8 @@ static void intel_disable_hdmi(struct intel_encoder *encoder, * doing the workaround. Sweep them under the rug. */ intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); + intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, + false); temp &= ~SDVO_PIPE_B_SELECT; temp |= SDVO_ENABLE; @@ -1172,7 +1173,8 @@ static void intel_disable_hdmi(struct intel_encoder *encoder, intel_wait_for_vblank_if_active(dev_priv, PIPE_A); intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); + intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, + true); } intel_hdmi->set_infoframes(&encoder->base, false, old_crtc_state, old_conn_state); diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c index 2ad13903a054..0568a9950f7f 100644 --- a/drivers/gpu/drm/i915/intel_sdvo.c +++ b/drivers/gpu/drm/i915/intel_sdvo.c @@ -1462,7 +1462,8 @@ static void intel_disable_sdvo(struct intel_encoder *encoder, * doing the workaround. Sweep them under the rug. */ intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); + intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, + false); temp &= ~SDVO_PIPE_B_SELECT; temp |= SDVO_ENABLE; @@ -1473,7 +1474,8 @@ static void intel_disable_sdvo(struct intel_encoder *encoder, intel_wait_for_vblank_if_active(dev_priv, PIPE_A); intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); - intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); + intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A, + true); } }