From patchwork Thu May 4 11:41:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maarten Lankhorst X-Patchwork-Id: 9711495 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7361260235 for ; Thu, 4 May 2017 11:41:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5BED328686 for ; Thu, 4 May 2017 11:41:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 50D9D2868C; Thu, 4 May 2017 11:41:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D24B228686 for ; Thu, 4 May 2017 11:41:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id EB7726E4E6; Thu, 4 May 2017 11:41:56 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mblankhorst.nl (mblankhorst.nl [IPv6:2a02:2308::216:3eff:fe92:dfa3]) by gabe.freedesktop.org (Postfix) with ESMTPS id C39426E1AF for ; Thu, 4 May 2017 11:41:48 +0000 (UTC) From: Maarten Lankhorst To: intel-gfx@lists.freedesktop.org Date: Thu, 4 May 2017 13:41:28 +0200 Message-Id: <20170504114133.4843-3-maarten.lankhorst@linux.intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170504114133.4843-1-maarten.lankhorst@linux.intel.com> References: <20170504114133.4843-1-maarten.lankhorst@linux.intel.com> Subject: [Intel-gfx] [RFC 2/7] drm/i915: Program gen3- watermarks atomically X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP With the atomic watermark calculations calculate intermediary watermark values and update the watermarks atomically. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/i915_drv.h | 5 ++ drivers/gpu/drm/i915/intel_drv.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 103 +++++++++++++++++++++++++++++++++------ 3 files changed, 95 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 91b945cd39f9..7af4f908b2cd 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1793,6 +1793,10 @@ struct g4x_wm_values { bool fbc_en; }; +struct i9xx_wm_values { + bool cxsr; +}; + struct skl_ddb_entry { uint16_t start, end; /* in number of blocks, 'end' is exclusive */ }; @@ -2422,6 +2426,7 @@ struct drm_i915_private { struct skl_wm_values skl_hw; struct vlv_wm_values vlv; struct g4x_wm_values g4x; + struct i9xx_wm_values i9xx; }; uint8_t max_level; diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d9e49f2b3c22..73e74fc7383c 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -600,7 +600,7 @@ struct intel_crtc_wm_state { struct g4x_wm_state optimal; } g4x; struct { - struct i9xx_wm_state optimal; + struct i9xx_wm_state optimal, intermediate; } i9xx; }; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0c933cfad02c..c39f63aff4a5 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -433,6 +433,8 @@ bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) dev_priv->wm.vlv.cxsr = enable; else if (IS_G4X(dev_priv)) dev_priv->wm.g4x.cxsr = enable; + else if (INTEL_GEN(dev_priv) <= 4) + dev_priv->wm.i9xx.cxsr = enable; mutex_unlock(&dev_priv->wm.wm_mutex); return ret; @@ -2317,6 +2319,44 @@ static int i9xx_compute_pipe_wm(struct intel_crtc_state *crtc_state) return 0; } +static int i9xx_compute_intermediate_wm(struct drm_device *dev, + struct intel_crtc *intel_crtc, + struct intel_crtc_state *newstate) +{ + struct i9xx_wm_state *intermediate = &newstate->wm.i9xx.intermediate; + const struct drm_crtc_state *old_drm_state = + drm_atomic_get_old_crtc_state(newstate->base.state, &intel_crtc->base); + const struct i9xx_wm_state *old = &to_intel_crtc_state(old_drm_state)->wm.i9xx.optimal; + const struct i9xx_wm_state *optimal = &newstate->wm.i9xx.optimal; + + /* + * Start with the final, target watermarks, then combine with the + * currently active watermarks to get values that are safe both before + * and after the vblank. + */ + *intermediate = *optimal; + if (newstate->disable_cxsr) + intermediate->cxsr = false; + + if (!newstate->base.active || + drm_atomic_crtc_needs_modeset(&newstate->base)) + goto out; + + intermediate->plane_wm = min(old->plane_wm, optimal->plane_wm); + intermediate->sr.plane = min(old->sr.plane, optimal->sr.plane); + +out: + /* + * If our intermediate WM are identical to the final WM, then we can + * omit the post-vblank programming; only update if it's different. + */ + if (newstate->base.active && + memcmp(intermediate, optimal, sizeof(*intermediate)) != 0) + newstate->wm.need_postvbl_update = true; + + return 0; +} + void i9xx_wm_get_hw_state(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); @@ -2345,17 +2385,15 @@ void i9xx_wm_get_hw_state(struct drm_device *dev) } } -static void i9xx_update_wm(struct intel_crtc *crtc) +static void i9xx_program_watermarks(struct drm_i915_private *dev_priv) { - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct intel_crtc *crtc; uint32_t fwater_lo; uint32_t fwater_hi; int cwm, srwm = -1; int planea_wm, planeb_wm; struct intel_crtc *enabled = NULL; - crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal; - crtc = intel_get_crtc_for_plane(dev_priv, 0); planea_wm = crtc->wm.active.i9xx.plane_wm; if (intel_crtc_active(crtc)) @@ -2381,7 +2419,7 @@ static void i9xx_update_wm(struct intel_crtc *crtc) cwm = 2; /* Play safe and disable self-refresh before adjusting watermarks. */ - intel_set_memory_cxsr(dev_priv, false); + _intel_set_memory_cxsr(dev_priv, false); /* Calc sr entries for one plane configs */ if (enabled) { @@ -2408,19 +2446,17 @@ static void i9xx_update_wm(struct intel_crtc *crtc) I915_WRITE(FW_BLC2, fwater_hi); if (enabled) - intel_set_memory_cxsr(dev_priv, true); + _intel_set_memory_cxsr(dev_priv, true); + + dev_priv->wm.i9xx.cxsr = enabled; } -static void i845_update_wm(struct intel_crtc *crtc) +static void i845_program_watermarks(struct intel_crtc *crtc) { struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); uint32_t fwater_lo; int planea_wm; - if (!intel_crtc_active(crtc)) - return; - - crtc->wm.active.i9xx = crtc->config->wm.i9xx.optimal; planea_wm = crtc->wm.active.i9xx.plane_wm; fwater_lo = I915_READ(FW_BLC) & ~0xfff; @@ -2431,6 +2467,41 @@ static void i845_update_wm(struct intel_crtc *crtc) I915_WRITE(FW_BLC, fwater_lo); } + +static void i9xx_initial_watermarks(struct intel_atomic_state *state, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); + + mutex_lock(&dev_priv->wm.wm_mutex); + crtc->wm.active.i9xx = crtc_state->wm.i9xx.intermediate; + if (INTEL_INFO(dev_priv)->num_pipes == 1) + i845_program_watermarks(intel_crtc); + else + i9xx_program_watermarks(dev_priv); + mutex_unlock(&dev_priv->wm.wm_mutex); +} + +static void i9xx_optimize_watermarks(struct intel_atomic_state *state, + struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); + struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); + + if (!crtc_state->wm.need_postvbl_update) + return; + + mutex_lock(&dev_priv->wm.wm_mutex); + intel_crtc->wm.active.i9xx = crtc_state->wm.i9xx.optimal; + if (INTEL_INFO(dev_priv)->num_pipes == 1) + i845_program_watermarks(intel_crtc); + else + i9xx_program_watermarks(dev_priv); + mutex_unlock(&dev_priv->wm.wm_mutex); +} + /* latency must be in 0.1us units. */ static unsigned int ilk_wm_method1(unsigned int pixel_rate, unsigned int cpp, @@ -8743,17 +8814,21 @@ void intel_init_pm(struct drm_i915_private *dev_priv) dev_priv->display.update_wm = i965_update_wm; } else if (IS_GEN3(dev_priv)) { dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm; - dev_priv->display.update_wm = i9xx_update_wm; + dev_priv->display.compute_intermediate_wm = i9xx_compute_intermediate_wm; + + dev_priv->display.initial_watermarks = i9xx_initial_watermarks; + dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks; dev_priv->display.get_fifo_size = i9xx_get_fifo_size; } else if (IS_GEN2(dev_priv)) { dev_priv->display.compute_pipe_wm = i9xx_compute_pipe_wm; + dev_priv->display.compute_intermediate_wm = i9xx_compute_intermediate_wm; + dev_priv->display.initial_watermarks = i9xx_initial_watermarks; + dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks; if (INTEL_INFO(dev_priv)->num_pipes == 1) { - dev_priv->display.update_wm = i845_update_wm; dev_priv->display.get_fifo_size = i845_get_fifo_size; } else { - dev_priv->display.update_wm = i9xx_update_wm; dev_priv->display.get_fifo_size = i830_get_fifo_size; } } else {