From patchwork Thu May 4 11:41:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maarten Lankhorst X-Patchwork-Id: 9711485 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8811160235 for ; Thu, 4 May 2017 11:41:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 70E9C28689 for ; Thu, 4 May 2017 11:41:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 65A1D2868A; Thu, 4 May 2017 11:41:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E2D5828691 for ; Thu, 4 May 2017 11:41:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 73AB86E4B5; Thu, 4 May 2017 11:41:50 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mblankhorst.nl (mblankhorst.nl [141.105.120.124]) by gabe.freedesktop.org (Postfix) with ESMTPS id 259076E089 for ; Thu, 4 May 2017 11:41:49 +0000 (UTC) From: Maarten Lankhorst To: intel-gfx@lists.freedesktop.org Date: Thu, 4 May 2017 13:41:29 +0200 Message-Id: <20170504114133.4843-4-maarten.lankhorst@linux.intel.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170504114133.4843-1-maarten.lankhorst@linux.intel.com> References: <20170504114133.4843-1-maarten.lankhorst@linux.intel.com> Subject: [Intel-gfx] [RFC 3/7] drm/i915: Convert pineview watermarks to atomic X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Pineview seems to have different watermarks from the other platforms and are calculated separately. Signed-off-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_drv.h | 3 +- drivers/gpu/drm/i915/intel_pm.c | 134 ++++++++++++++++++++++++++------------- 2 files changed, 92 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 73e74fc7383c..62f690c7691e 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -552,7 +552,8 @@ struct i9xx_wm_state { struct { uint16_t plane; - } sr; + uint16_t cursor; + } sr, hpll; }; struct intel_crtc_wm_state { diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index c39f63aff4a5..eb1bb8b3f9a6 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -824,13 +824,17 @@ static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv) return enabled; } -static void pineview_update_wm(struct intel_crtc *unused_crtc) +static int pnv_compute_pipe_wm(struct intel_crtc_state *crtc_state) { - struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); - struct intel_crtc *crtc; + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + struct i9xx_wm_state *wm_state = &crtc_state->wm.i9xx.optimal; + struct intel_plane *plane = to_intel_plane(crtc->base.primary); + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->base.state); + const struct drm_plane_state *primary_plane_state = NULL; const struct cxsr_latency *latency; - u32 reg; - unsigned int wm; + + memset(wm_state, 0, sizeof(*wm_state)); latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv), dev_priv->is_ddr3, @@ -838,60 +842,90 @@ static void pineview_update_wm(struct intel_crtc *unused_crtc) dev_priv->mem_freq); if (!latency) { DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); - intel_set_memory_cxsr(dev_priv, false); - return; + + return 0; } - crtc = single_enabled_crtc(dev_priv); - if (crtc) { - const struct drm_display_mode *adjusted_mode = - &crtc->config->base.adjusted_mode; + if (crtc_state->base.plane_mask & BIT(drm_plane_index(&plane->base))) + primary_plane_state = __drm_atomic_get_current_plane_state(&state->base, &plane->base); + + if (primary_plane_state) { const struct drm_framebuffer *fb = - crtc->base.primary->state->fb; + primary_plane_state->fb; int cpp = fb->format->cpp[0]; - int clock = adjusted_mode->crtc_clock; + const struct drm_display_mode *adjusted_mode = + &crtc_state->base.adjusted_mode; + unsigned active_crtcs; + + if (state->modeset) + active_crtcs = state->active_crtcs; + else + active_crtcs = dev_priv->active_crtcs; + + wm_state->cxsr = active_crtcs == drm_crtc_mask(&crtc->base); + + wm_state->sr.plane = intel_calculate_wm(adjusted_mode->crtc_clock, + &pineview_display_wm, + pineview_display_wm.fifo_size, + cpp, latency->display_sr); + + wm_state->sr.cursor = intel_calculate_wm(adjusted_mode->crtc_clock, + &pineview_cursor_wm, + pineview_display_wm.fifo_size, + 4, latency->cursor_sr); + + wm_state->hpll.plane = intel_calculate_wm(adjusted_mode->crtc_clock, + &pineview_display_hplloff_wm, + pineview_display_hplloff_wm.fifo_size, + cpp, latency->display_hpll_disable); + + wm_state->hpll.cursor = intel_calculate_wm(adjusted_mode->crtc_clock, + &pineview_cursor_hplloff_wm, + pineview_display_hplloff_wm.fifo_size, + 4, latency->cursor_hpll_disable); + + DRM_DEBUG_KMS("FIFO watermarks - can cxsr: %s, display plane %d, cursor SR size: %d\n", + yesno(wm_state->cxsr), wm_state->sr.plane, wm_state->sr.cursor); + } else + wm_state->cxsr = false; + + return 0; +} + +static void pnv_program_watermarks(struct drm_i915_private *dev_priv) +{ + struct intel_crtc *crtc; + struct i9xx_wm_state *wm_state = NULL; + + crtc = single_enabled_crtc(dev_priv); + if (crtc) + wm_state = &crtc->wm.active.i9xx; + + if (wm_state && wm_state->cxsr) { + u32 reg; /* Display SR */ - wm = intel_calculate_wm(clock, &pineview_display_wm, - pineview_display_wm.fifo_size, - cpp, latency->display_sr); reg = I915_READ(DSPFW1); reg &= ~DSPFW_SR_MASK; - reg |= FW_WM(wm, SR); + reg |= FW_WM(wm_state->sr.plane, SR); I915_WRITE(DSPFW1, reg); DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); /* cursor SR */ - wm = intel_calculate_wm(clock, &pineview_cursor_wm, - pineview_display_wm.fifo_size, - 4, latency->cursor_sr); reg = I915_READ(DSPFW3); - reg &= ~DSPFW_CURSOR_SR_MASK; - reg |= FW_WM(wm, CURSOR_SR); + reg &= ~(DSPFW_CURSOR_SR_MASK | DSPFW_HPLL_SR_MASK | DSPFW_HPLL_CURSOR_MASK); + reg |= FW_WM(wm_state->sr.cursor, CURSOR_SR); + reg |= FW_WM(wm_state->hpll.plane, HPLL_SR); + reg |= FW_WM(wm_state->hpll.cursor, HPLL_SR); I915_WRITE(DSPFW3, reg); - /* Display HPLL off SR */ - wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, - pineview_display_hplloff_wm.fifo_size, - cpp, latency->display_hpll_disable); - reg = I915_READ(DSPFW3); - reg &= ~DSPFW_HPLL_SR_MASK; - reg |= FW_WM(wm, HPLL_SR); - I915_WRITE(DSPFW3, reg); - - /* cursor HPLL off SR */ - wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, - pineview_display_hplloff_wm.fifo_size, - 4, latency->cursor_hpll_disable); - reg = I915_READ(DSPFW3); - reg &= ~DSPFW_HPLL_CURSOR_MASK; - reg |= FW_WM(wm, HPLL_CURSOR); - I915_WRITE(DSPFW3, reg); DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); intel_set_memory_cxsr(dev_priv, true); + dev_priv->wm.i9xx.cxsr = true; } else { intel_set_memory_cxsr(dev_priv, false); + dev_priv->wm.i9xx.cxsr = false; } } @@ -2344,6 +2378,9 @@ static int i9xx_compute_intermediate_wm(struct drm_device *dev, intermediate->plane_wm = min(old->plane_wm, optimal->plane_wm); intermediate->sr.plane = min(old->sr.plane, optimal->sr.plane); + intermediate->sr.cursor = min(old->sr.cursor, optimal->sr.cursor); + intermediate->hpll.plane = min(old->hpll.plane, optimal->hpll.plane); + intermediate->hpll.cursor = min(old->hpll.cursor, optimal->hpll.cursor); out: /* @@ -2477,7 +2514,9 @@ static void i9xx_initial_watermarks(struct intel_atomic_state *state, mutex_lock(&dev_priv->wm.wm_mutex); crtc->wm.active.i9xx = crtc_state->wm.i9xx.intermediate; - if (INTEL_INFO(dev_priv)->num_pipes == 1) + if (IS_PINEVIEW(dev_priv)) + pnv_program_watermarks(dev_priv); + else if (INTEL_INFO(dev_priv)->num_pipes == 1) i845_program_watermarks(intel_crtc); else i9xx_program_watermarks(dev_priv); @@ -2495,7 +2534,9 @@ static void i9xx_optimize_watermarks(struct intel_atomic_state *state, mutex_lock(&dev_priv->wm.wm_mutex); intel_crtc->wm.active.i9xx = crtc_state->wm.i9xx.optimal; - if (INTEL_INFO(dev_priv)->num_pipes == 1) + if (IS_PINEVIEW(dev_priv)) + pnv_program_watermarks(dev_priv); + else if (INTEL_INFO(dev_priv)->num_pipes == 1) i845_program_watermarks(intel_crtc); else i9xx_program_watermarks(dev_priv); @@ -8807,9 +8848,14 @@ void intel_init_pm(struct drm_i915_private *dev_priv) dev_priv->fsb_freq, dev_priv->mem_freq); /* Disable CxSR and never update its watermark again */ intel_set_memory_cxsr(dev_priv, false); - dev_priv->display.update_wm = NULL; - } else - dev_priv->display.update_wm = pineview_update_wm; + dev_priv->display.compute_pipe_wm = NULL; + dev_priv->display.initial_watermarks = NULL; + dev_priv->display.optimize_watermarks = NULL; + } else { + dev_priv->display.compute_pipe_wm = pnv_compute_pipe_wm; + dev_priv->display.initial_watermarks = i9xx_initial_watermarks; + dev_priv->display.optimize_watermarks = i9xx_optimize_watermarks; + } } else if (IS_GEN4(dev_priv)) { dev_priv->display.update_wm = i965_update_wm; } else if (IS_GEN3(dev_priv)) {