diff mbox

drm/i915: Exclude top-page for ppgtt as well as ggtt

Message ID 20170512174909.1063-1-chris@chris-wilson.co.uk (mailing list archive)
State New, archived
Headers show

Commit Message

Chris Wilson May 12, 2017, 5:49 p.m. UTC
We have always excluded the top-page of the Global GTT to prevent
prefetching past the end of the address space. We have been lax about
applying this restriction to the per-process GTT, but there is no reason
to believe that the hw restriction is any less severe.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Comments

Chris Wilson May 12, 2017, 5:55 p.m. UTC | #1
On Fri, May 12, 2017 at 06:49:09PM +0100, Chris Wilson wrote:
> We have always excluded the top-page of the Global GTT to prevent
> prefetching past the end of the address space. We have been lax about
> applying this restriction to the per-process GTT, but there is no reason
> to believe that the hw restriction is any less severe.

Other than empirical, but the note in bspec is still there and who knows
they may start to be strict again in future.
-Chris
Matthew Auld May 12, 2017, 7:01 p.m. UTC | #2
On 12 May 2017 at 18:49, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> We have always excluded the top-page of the Global GTT to prevent
> prefetching past the end of the address space. We have been lax about
> applying this restriction to the per-process GTT, but there is no reason
> to believe that the hw restriction is any less severe.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Chris Wilson May 12, 2017, 7:06 p.m. UTC | #3
On Fri, May 12, 2017 at 06:55:35PM +0100, Chris Wilson wrote:
> On Fri, May 12, 2017 at 06:49:09PM +0100, Chris Wilson wrote:
> > We have always excluded the top-page of the Global GTT to prevent
> > prefetching past the end of the address space. We have been lax about
> > applying this restriction to the per-process GTT, but there is no reason
> > to believe that the hw restriction is any less severe.
> 
> Other than empirical, but the note in bspec is still there and who knows
> they may start to be strict again in future.

Fwiw, it looks like we can sleep on this again. Jason no longer believes
this to be an immediate issue.
-Chris
Michel Thierry May 12, 2017, 8:26 p.m. UTC | #4
On 12/05/17 12:06, Chris Wilson wrote:
> On Fri, May 12, 2017 at 06:55:35PM +0100, Chris Wilson wrote:
>> On Fri, May 12, 2017 at 06:49:09PM +0100, Chris Wilson wrote:
>>> We have always excluded the top-page of the Global GTT to prevent
>>> prefetching past the end of the address space. We have been lax about
>>> applying this restriction to the per-process GTT, but there is no reason
>>> to believe that the hw restriction is any less severe.
>>
>> Other than empirical, but the note in bspec is still there and who knows
>> they may start to be strict again in future.
>
> Fwiw, it looks like we can sleep on this again. Jason no longer believes
> this to be an immediate issue.
> -Chris
>

It might be true for 32b ppgtt, but anything slightly recent should 
already be using 48b.

-Michel
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 5332d8cb1c53..f18ca11a8da6 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -1860,7 +1860,8 @@  static void i915_address_space_init(struct i915_address_space *vm,
 {
 	i915_gem_timeline_init(dev_priv, &vm->timeline, name);
 
-	drm_mm_init(&vm->mm, 0, vm->total);
+	/* Always exclude the top page to avoid prefetches past the end. */
+	drm_mm_init(&vm->mm, 0, vm->total - I915_GTT_PAGE_SIZE);
 	vm->mm.head_node.color = I915_COLOR_UNEVICTABLE;
 
 	INIT_LIST_HEAD(&vm->active_list);
@@ -2390,7 +2391,7 @@  static void i915_gtt_color_adjust(const struct drm_mm_node *node,
 	 * GTT boundary.
 	 */
 	node = list_next_entry(node, node_list);
-	if (node->color != color)
+	if (node->allocated && node->color != color)
 		*end -= I915_GTT_PAGE_SIZE;
 }