From patchwork Fri May 26 11:56:02 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lionel Landwerlin X-Patchwork-Id: 9750463 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 90B4160209 for ; Fri, 26 May 2017 11:56:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8647C2833C for ; Fri, 26 May 2017 11:56:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7B3EC283D2; Fri, 26 May 2017 11:56:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E21222833C for ; Fri, 26 May 2017 11:56:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F16186ECF2; Fri, 26 May 2017 11:56:29 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 668526ECED for ; Fri, 26 May 2017 11:56:28 +0000 (UTC) Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP; 26 May 2017 04:56:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.38,397,1491289200"; d="scan'208";a="107319708" Received: from delly.ld.intel.com ([10.103.239.215]) by fmsmga006.fm.intel.com with ESMTP; 26 May 2017 04:56:25 -0700 From: Lionel Landwerlin To: intel-gfx@lists.freedesktop.org Date: Fri, 26 May 2017 12:56:02 +0100 Message-Id: <20170526115615.9928-2-lionel.g.landwerlin@intel.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20170526115615.9928-1-lionel.g.landwerlin@intel.com> References: <20170424071751.2416-1-lionel.g.landwerlin@intel.com> <20170526115615.9928-1-lionel.g.landwerlin@intel.com> Subject: [Intel-gfx] [PATCH v14 01/14] drm/i915: Record both min/max eu_per_subslice in sseu_dev_info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Chris Wilson When we query the available eu on each subslice, we currently only report the max. It would also be useful to report the minimum found as well. When we set RPCS (power gating over the EU), we can also specify both the min and max number of eu to configure on each slice; currently we just set it to a single value, but the flexibility may be beneficial in future. Signed-off-by: Chris Wilson Signed-off-by: Lionel Landwerlin Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_debugfs.c | 36 +++++++++++++++++++++++--------- drivers/gpu/drm/i915/i915_drv.h | 3 ++- drivers/gpu/drm/i915/intel_device_info.c | 32 +++++++++++++++++----------- drivers/gpu/drm/i915/intel_lrc.c | 4 ++-- 4 files changed, 50 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index c08a6d8a4e07..149214ba36c3 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -4489,6 +4489,7 @@ DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops, static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, struct sseu_dev_info *sseu) { + unsigned int min_eu_per_subslice, max_eu_per_subslice; int ss_max = 2; int ss; u32 sig1[ss_max], sig2[ss_max]; @@ -4498,6 +4499,9 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, sig2[0] = I915_READ(CHV_POWER_SS0_SIG2); sig2[1] = I915_READ(CHV_POWER_SS1_SIG2); + min_eu_per_subslice = ~0u; + max_eu_per_subslice = 0; + for (ss = 0; ss < ss_max; ss++) { unsigned int eu_cnt; @@ -4512,14 +4516,18 @@ static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv, ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) + ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2); sseu->eu_total += eu_cnt; - sseu->eu_per_subslice = max_t(unsigned int, - sseu->eu_per_subslice, eu_cnt); + min_eu_per_subslice = min(min_eu_per_subslice, eu_cnt); + max_eu_per_subslice = max(max_eu_per_subslice, eu_cnt); } + + sseu->min_eu_per_subslice = min_eu_per_subslice; + sseu->max_eu_per_subslice = max_eu_per_subslice; } static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, struct sseu_dev_info *sseu) { + unsigned int min_eu_per_subslice, max_eu_per_subslice; int s_max = 3, ss_max = 4; int s, ss; u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2]; @@ -4545,6 +4553,9 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, GEN9_PGCTL_SSB_EU210_ACK | GEN9_PGCTL_SSB_EU311_ACK; + min_eu_per_subslice = ~0u; + max_eu_per_subslice = 0; + for (s = 0; s < s_max; s++) { if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0) /* skip disabled slice */ @@ -4570,11 +4581,14 @@ static void gen9_sseu_device_status(struct drm_i915_private *dev_priv, eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] & eu_mask[ss%2]); sseu->eu_total += eu_cnt; - sseu->eu_per_subslice = max_t(unsigned int, - sseu->eu_per_subslice, - eu_cnt); + + min_eu_per_subslice = min(min_eu_per_subslice, eu_cnt); + max_eu_per_subslice = max(max_eu_per_subslice, eu_cnt); } } + + sseu->min_eu_per_subslice = min_eu_per_subslice; + sseu->max_eu_per_subslice = max_eu_per_subslice; } static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, @@ -4587,9 +4601,11 @@ static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv, if (sseu->slice_mask) { sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask; - sseu->eu_per_subslice = - INTEL_INFO(dev_priv)->sseu.eu_per_subslice; - sseu->eu_total = sseu->eu_per_subslice * + sseu->min_eu_per_subslice = + INTEL_INFO(dev_priv)->sseu.min_eu_per_subslice; + sseu->max_eu_per_subslice = + INTEL_INFO(dev_priv)->sseu.max_eu_per_subslice; + sseu->eu_total = sseu->max_eu_per_subslice * sseu_subslice_total(sseu); /* subtract fused off EU(s) from enabled slice(s) */ @@ -4620,8 +4636,8 @@ static void i915_print_sseu_info(struct seq_file *m, bool is_available_info, hweight8(sseu->subslice_mask)); seq_printf(m, " %s EU Total: %u\n", type, sseu->eu_total); - seq_printf(m, " %s EU Per Subslice: %u\n", type, - sseu->eu_per_subslice); + seq_printf(m, " %s EU Per Subslice: [%u, %u]\n", type, + sseu->min_eu_per_subslice, sseu->max_eu_per_subslice); if (!is_available_info) return; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9ba22427c05c..7faad0ea18a8 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -783,7 +783,8 @@ struct sseu_dev_info { u8 slice_mask; u8 subslice_mask; u8 eu_total; - u8 eu_per_subslice; + u8 min_eu_per_subslice; + u8 max_eu_per_subslice; u8 min_eu_in_pool; /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ u8 subslice_7eu[3]; diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 3718341662c2..f21f597c5cb9 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -83,6 +83,7 @@ void intel_device_info_dump(struct drm_i915_private *dev_priv) static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) { struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; + unsigned int eu_per_subslice; u32 fuse, eu_dis; fuse = I915_READ(CHV_FUSE_GT); @@ -107,9 +108,10 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) * CHV expected to always have a uniform distribution of EU * across subslices. */ - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? - sseu->eu_total / sseu_subslice_total(sseu) : - 0; + eu_per_subslice = sseu_subslice_total(sseu) ? + sseu->eu_total / sseu_subslice_total(sseu) : 0; + sseu->min_eu_per_subslice = eu_per_subslice; + sseu->max_eu_per_subslice = eu_per_subslice; /* * CHV supports subslice power gating on devices with more than * one subslice, and supports EU power gating on devices with @@ -117,13 +119,14 @@ static void cherryview_sseu_info_init(struct drm_i915_private *dev_priv) */ sseu->has_slice_pg = 0; sseu->has_subslice_pg = sseu_subslice_total(sseu) > 1; - sseu->has_eu_pg = (sseu->eu_per_subslice > 2); + sseu->has_eu_pg = eu_per_subslice > 2; } static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) { struct intel_device_info *info = mkwrite_device_info(dev_priv); struct sseu_dev_info *sseu = &info->sseu; + unsigned int eu_per_subslice; int s_max = 3, ss_max = 4, eu_max = 8; int s, ss; u32 fuse2, eu_disable; @@ -179,9 +182,10 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) * recovery. BXT is expected to be perfectly uniform in EU * distribution. */ - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? - DIV_ROUND_UP(sseu->eu_total, - sseu_subslice_total(sseu)) : 0; + eu_per_subslice = sseu_subslice_total(sseu) ? + DIV_ROUND_UP(sseu->eu_total, sseu_subslice_total(sseu)) : 0; + sseu->min_eu_per_subslice = eu_per_subslice; + sseu->max_eu_per_subslice = eu_per_subslice; /* * SKL supports slice power gating on devices with more than * one slice, and supports EU power gating on devices with @@ -195,7 +199,7 @@ static void gen9_sseu_info_init(struct drm_i915_private *dev_priv) hweight8(sseu->slice_mask) > 1; sseu->has_subslice_pg = IS_GEN9_LP(dev_priv) && sseu_subslice_total(sseu) > 1; - sseu->has_eu_pg = sseu->eu_per_subslice > 2; + sseu->has_eu_pg = eu_per_subslice > 2; if (IS_GEN9_LP(dev_priv)) { #define IS_SS_DISABLED(ss) (!(sseu->subslice_mask & BIT(ss))) @@ -228,6 +232,7 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) { struct sseu_dev_info *sseu = &mkwrite_device_info(dev_priv)->sseu; const int s_max = 3, ss_max = 3, eu_max = 8; + unsigned int eu_per_subslice; int s, ss; u32 fuse2, eu_disable[3]; /* s_max */ @@ -282,9 +287,10 @@ static void broadwell_sseu_info_init(struct drm_i915_private *dev_priv) * subslices with the exception that any one EU in any one subslice may * be fused off for die recovery. */ - sseu->eu_per_subslice = sseu_subslice_total(sseu) ? - DIV_ROUND_UP(sseu->eu_total, - sseu_subslice_total(sseu)) : 0; + eu_per_subslice = sseu_subslice_total(sseu) ? + DIV_ROUND_UP(sseu->eu_total, sseu_subslice_total(sseu)) : 0; + sseu->min_eu_per_subslice = eu_per_subslice; + sseu->max_eu_per_subslice = eu_per_subslice; /* * BDW supports slice power gating on devices with more than @@ -421,7 +427,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) DRM_DEBUG_DRIVER("subslice per slice: %u\n", hweight8(info->sseu.subslice_mask)); DRM_DEBUG_DRIVER("EU total: %u\n", info->sseu.eu_total); - DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->sseu.eu_per_subslice); + DRM_DEBUG_DRIVER("EU per subslice: [%u, %u]\n", + info->sseu.min_eu_per_subslice, + info->sseu.max_eu_per_subslice); DRM_DEBUG_DRIVER("has slice power gating: %s\n", info->sseu.has_slice_pg ? "y" : "n"); DRM_DEBUG_DRIVER("has subslice power gating: %s\n", diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 014b30ace8a0..9a279a559a0f 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1843,9 +1843,9 @@ make_rpcs(struct drm_i915_private *dev_priv) } if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { - rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << + rpcs |= INTEL_INFO(dev_priv)->sseu.min_eu_per_subslice << GEN8_RPCS_EU_MIN_SHIFT; - rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << + rpcs |= INTEL_INFO(dev_priv)->sseu.max_eu_per_subslice << GEN8_RPCS_EU_MAX_SHIFT; rpcs |= GEN8_RPCS_ENABLE; }