From patchwork Wed May 31 18:52:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 9757969 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7D6A4602BF for ; Wed, 31 May 2017 18:52:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7150F2834A for ; Wed, 31 May 2017 18:52:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 62F8B284BB; Wed, 31 May 2017 18:52:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 791052834A for ; Wed, 31 May 2017 18:52:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8F7176E2EF; Wed, 31 May 2017 18:52:32 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 372186E2E8 for ; Wed, 31 May 2017 18:52:28 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 May 2017 11:52:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.39,275,1493708400"; d="scan'208"; a="1155033227" Received: from sgallagh-mobl1.ger.corp.intel.com (HELO mwahaha.ger.corp.intel.com) ([10.252.0.34]) by fmsmga001.fm.intel.com with ESMTP; 31 May 2017 11:52:25 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Wed, 31 May 2017 19:52:06 +0100 Message-Id: <20170531185210.29189-12-matthew.auld@intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170531185210.29189-1-matthew.auld@intel.com> References: <20170531185210.29189-1-matthew.auld@intel.com> Subject: [Intel-gfx] [PATCH 11/15] drm/i915: accurate page size tracking for the ppgtt X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Now that we support multiple page sizes for the ppgtt, it would be useful to track the real usage for debugging purposes. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_gtt.c | 10 ++++++++++ drivers/gpu/drm/i915/i915_gem_object.h | 2 ++ drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 1 + 3 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 924aec4adf6d..84de1618594e 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -217,6 +217,8 @@ static int ppgtt_bind_vma(struct i915_vma *vma, static void ppgtt_unbind_vma(struct i915_vma *vma) { vma->vm->clear_range(vma->vm, vma->node.start, vma->size); + + vma->obj->mm.page_sizes.gtt = 0; } static gen8_pte_t gen8_pte_encode(dma_addr_t addr, @@ -924,6 +926,8 @@ static void gen8_ppgtt_insert_3lvl(struct i915_address_space *vm, gen8_ppgtt_insert_pte_entries(ppgtt, &ppgtt->pdp, &iter, &idx, cache_level); + + page_sizes->gtt = I915_GTT_PAGE_SIZE; } static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, @@ -972,6 +976,8 @@ static void gen8_ppgtt_insert_4lvl(struct i915_address_space *vm, } } + page_sizes->gtt |= page_size; + start += page_size; iter.dma += page_size; if (iter.dma >= iter.max) { @@ -1731,6 +1737,8 @@ static void gen6_ppgtt_insert_entries(struct i915_address_space *vm, } } while (1); kunmap_atomic(vaddr); + + page_sizes->gtt = I915_GTT_PAGE_SIZE; } static int gen6_alloc_va_range(struct i915_address_space *vm, @@ -2525,6 +2533,8 @@ static void aliasing_gtt_unbind_vma(struct i915_vma *vma) struct i915_address_space *vm = &i915->mm.aliasing_ppgtt->base; vm->clear_range(vm, vma->node.start, vma->size); + + vma->obj->mm.page_sizes.gtt = 0; } } diff --git a/drivers/gpu/drm/i915/i915_gem_object.h b/drivers/gpu/drm/i915/i915_gem_object.h index 6db34eac9794..9b00947bf856 100644 --- a/drivers/gpu/drm/i915/i915_gem_object.h +++ b/drivers/gpu/drm/i915/i915_gem_object.h @@ -129,9 +129,11 @@ struct drm_i915_gem_object { struct sg_table *pages; void *mapping; + /* TODO: whack some of this into the error state */ struct i915_page_sizes { unsigned int phys; unsigned int sg; + unsigned int gtt; } page_sizes; struct i915_gem_object_page_iter { diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c index 81c0d6b87e68..954f4140d902 100644 --- a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c @@ -267,6 +267,7 @@ static int lowlevel_hole(struct drm_i915_private *i915, GEM_BUG_ON(addr + BIT_ULL(size) > vm->total); vm->clear_range(vm, addr, BIT_ULL(size)); + obj->mm.page_sizes.gtt = 0; } i915_gem_object_unpin_pages(obj);