From patchwork Wed May 31 18:52:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 9757961 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0C3A8602BF for ; Wed, 31 May 2017 18:52:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 00D572845E for ; Wed, 31 May 2017 18:52:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E9D1E2849E; Wed, 31 May 2017 18:52:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B027F2834A for ; Wed, 31 May 2017 18:52:24 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D55F16E2E1; Wed, 31 May 2017 18:52:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6CACD6E2DE for ; Wed, 31 May 2017 18:52:19 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 31 May 2017 11:52:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.39,275,1493708400"; d="scan'208"; a="1155033175" Received: from sgallagh-mobl1.ger.corp.intel.com (HELO mwahaha.ger.corp.intel.com) ([10.252.0.34]) by fmsmga001.fm.intel.com with ESMTP; 31 May 2017 11:52:18 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Wed, 31 May 2017 19:52:00 +0100 Message-Id: <20170531185210.29189-6-matthew.auld@intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170531185210.29189-1-matthew.auld@intel.com> References: <20170531185210.29189-1-matthew.auld@intel.com> Subject: [Intel-gfx] [PATCH 05/15] drm/i915: align the vma start to the largest gtt page size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP When inserting into a 48bit PPGTT we should the align the vma start address to the required page size boundary, to guarantee we use said page size in the gtt. If we are dealing with multiple page-sizes, we can't guarantee anything and just align to the largest. For soft pinning we don't force any alignment. Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_vma.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 1aba47024656..c355ccb01872 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -485,6 +485,18 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) if (ret) goto err_unpin; } else { + if (i915_vm_is_48bit(vma->vm) && + obj->mm.page_sizes.sg > I915_GTT_PAGE_SIZE) { + unsigned int page_alignment = obj->mm.page_sizes.sg; + + /* Align to the largest and hope for the best */ + if (!is_power_of_2(page_alignment)) + page_alignment = BIT(fls64(page_alignment)-1); + + alignment = max_t(typeof(alignment), alignment, + page_alignment); + } + ret = i915_gem_gtt_insert(vma->vm, &vma->node, size, alignment, obj->cache_level, start, end, flags);