From patchwork Tue Jun 13 19:33:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zanoni, Paulo R" X-Patchwork-Id: 9784505 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7DC6F6038E for ; Tue, 13 Jun 2017 19:34:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 72C8D2871B for ; Tue, 13 Jun 2017 19:34:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 67A8C28723; Tue, 13 Jun 2017 19:34:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 18F8028722 for ; Tue, 13 Jun 2017 19:34:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 65D776E382; Tue, 13 Jun 2017 19:34:04 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9DF076E364 for ; Tue, 13 Jun 2017 19:34:03 +0000 (UTC) Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by fmsmga101.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jun 2017 12:34:03 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,339,1493708400"; d="scan'208";a="113970089" Received: from przanoni-mobl.amr.corp.intel.com ([10.254.177.94]) by fmsmga005.fm.intel.com with ESMTP; 13 Jun 2017 12:34:02 -0700 From: Paulo Zanoni To: intel-gfx@lists.freedesktop.org Date: Tue, 13 Jun 2017 16:33:44 -0300 Message-Id: <20170613193350.10528-2-paulo.r.zanoni@intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170613193350.10528-1-paulo.r.zanoni@intel.com> References: <20170613193350.10528-1-paulo.r.zanoni@intel.com> Cc: Paulo Zanoni Subject: [Intel-gfx] [PATCH 1/7] drm/i915: reorder the register picking macros X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP We currently have pipe, plane, trans, port, pll and phy versions of these macros. Reorder their definitions so all macros of each type are in their own group, separated by blank lines. Signed-off-by: Paulo Zanoni Reviewed-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 88e4707..a1d3cca 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -52,19 +52,24 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a))) #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) +#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) + #define _PLANE(plane, a, b) _PIPE(plane, a, b) #define _MMIO_PLANE(plane, a, b) _MMIO_PIPE(plane, a, b) + #define _TRANS(tran, a, b) ((a) + (tran)*((b)-(a))) #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) + #define _PORT(port, a, b) ((a) + (port)*((b)-(a))) #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) -#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) -#define _PLL(pll, a, b) ((a) + (pll)*((b)-(a))) -#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) #define _MMIO_PORT6(port, a, b, c, d, e, f) _MMIO(_PICK(port, a, b, c, d, e, f)) #define _MMIO_PORT6_LN(port, ln, a0, a1, b, c, d, e, f) \ _MMIO(_PICK(port, a0, b, c, d, e, f) + (ln * (a1 - a0))) + +#define _PLL(pll, a, b) ((a) + (pll)*((b)-(a))) +#define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) + #define _PHY3(phy, ...) _PICK(phy, __VA_ARGS__) #define _MMIO_PHY3(phy, a, b, c) _MMIO(_PHY3(phy, a, b, c))