| Message ID | 20170613193350.10528-7-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, 13 Jun 2017, Paulo Zanoni <paulo.r.zanoni@intel.com> wrote: > Make sure all the macros are next to each other so it's easier to spot > all the options available. Please also move _MIPI_PORT and _MMIO_MIPI up. Btw they're another variant... BR, Jani. > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 14 ++++++-------- > 1 file changed, 6 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 3e46ba1..a97af4a 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -53,6 +53,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > > #define _PIPE(pipe, a, b) _PICK(pipe, a, b) > #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) > +#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ > + dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ > + dev_priv->info.display_mmio_offset) > #define _MMIO_PIPE3(pipe, ...) _MMIO(_PICK3(pipe, __VA_ARGS__)) > > #define _PLANE(plane, a, b) _PICK(plane, a, b) > @@ -60,6 +63,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > > #define _TRANS(tran, a, b) _PICK(tran, a, b) > #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) > +#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ > + dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ > + dev_priv->info.display_mmio_offset) > > #define _PORT(port, a, b) _PICK(port, a, b) > #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) > @@ -3700,10 +3706,6 @@ enum { > #define CHV_TRANSCODER_C_OFFSET 0x63000 > #define TRANSCODER_EDP_OFFSET 0x6f000 > > -#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ > - dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ > - dev_priv->info.display_mmio_offset) > - > #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) > #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) > #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) > @@ -5189,10 +5191,6 @@ enum { > */ > #define PIPE_EDP_OFFSET 0x7f000 > > -#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ > - dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ > - dev_priv->info.display_mmio_offset) > - > #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) > #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) > #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3e46ba1..a97af4a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -53,6 +53,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _PIPE(pipe, a, b) _PICK(pipe, a, b) #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) +#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ + dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ + dev_priv->info.display_mmio_offset) #define _MMIO_PIPE3(pipe, ...) _MMIO(_PICK3(pipe, __VA_ARGS__)) #define _PLANE(plane, a, b) _PICK(plane, a, b) @@ -60,6 +63,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define _TRANS(tran, a, b) _PICK(tran, a, b) #define _MMIO_TRANS(tran, a, b) _MMIO(_TRANS(tran, a, b)) +#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ + dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ + dev_priv->info.display_mmio_offset) #define _PORT(port, a, b) _PICK(port, a, b) #define _MMIO_PORT(port, a, b) _MMIO(_PORT(port, a, b)) @@ -3700,10 +3706,6 @@ enum { #define CHV_TRANSCODER_C_OFFSET 0x63000 #define TRANSCODER_EDP_OFFSET 0x6f000 -#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \ - dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \ - dev_priv->info.display_mmio_offset) - #define HTOTAL(trans) _MMIO_TRANS2(trans, _HTOTAL_A) #define HBLANK(trans) _MMIO_TRANS2(trans, _HBLANK_A) #define HSYNC(trans) _MMIO_TRANS2(trans, _HSYNC_A) @@ -5189,10 +5191,6 @@ enum { */ #define PIPE_EDP_OFFSET 0x7f000 -#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \ - dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \ - dev_priv->info.display_mmio_offset) - #define PIPECONF(pipe) _MMIO_PIPE2(pipe, _PIPEACONF) #define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) #define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH)
Make sure all the macros are next to each other so it's easier to spot all the options available. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-)