From patchwork Wed Jun 21 20:33:38 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 9802853 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3FC126038C for ; Wed, 21 Jun 2017 20:34:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3004C28512 for ; Wed, 21 Jun 2017 20:34:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 24AAC28554; Wed, 21 Jun 2017 20:34:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C950B28512 for ; Wed, 21 Jun 2017 20:34:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5BD4E6E598; Wed, 21 Jun 2017 20:34:05 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 71BEE6E58F for ; Wed, 21 Jun 2017 20:34:02 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP; 21 Jun 2017 13:34:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,370,1493708400"; d="scan'208";a="870413128" Received: from mutux-mobl.ger.corp.intel.com (HELO mwahaha.ger.corp.intel.com) ([10.252.23.195]) by FMSMGA003.fm.intel.com with ESMTP; 21 Jun 2017 13:34:00 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Wed, 21 Jun 2017 21:33:38 +0100 Message-Id: <20170621203345.26320-13-matthew.auld@intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170621203345.26320-1-matthew.auld@intel.com> References: <20170621203345.26320-1-matthew.auld@intel.com> Subject: [Intel-gfx] [PATCH 12/19] drm/i915: support 64K pages for the 48b PPGTT X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Matthew Auld Cc: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_gtt.c | 26 ++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_gem_gtt.h | 1 + 2 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index 03c35097ef39..9b89ec10f333 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -937,6 +937,7 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, struct i915_page_table *pt = pd->page_table[idx.pde]; dma_addr_t rem = iter->max - iter->dma; unsigned int page_size; + bool maybe_64K = false; gen8_pte_t encode = pte_encode; gen8_pte_t *vaddr; u16 index, max; @@ -962,9 +963,17 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, index = idx.pte; max = GEN8_PTES; page_size = I915_GTT_PAGE_SIZE; + + if (vma->page_sizes.sg & I915_GTT_PAGE_SIZE_64K && !idx.pte) + maybe_64K = true; } do { + if (maybe_64K && (index % 16 == 0) && + (!IS_ALIGNED(iter->dma, I915_GTT_PAGE_SIZE_64K) || + rem < I915_GTT_PAGE_SIZE_64K)) + maybe_64K = false; + vaddr[index++] = encode | iter->dma; start += page_size; @@ -986,6 +995,23 @@ static void gen8_ppgtt_insert_huge_entries(struct i915_vma *vma, kunmap_atomic(vaddr); + + /* Is it safe to mark the 2M block as 64K? -- Either we have + * filled whole page-table with 64K entries, or filled part of + * it and have reached the end of the sg table and we have + * enough padding. + */ + if (maybe_64K) { + if (index == max || + (!iter->sg && IS_ALIGNED(vma->node.start + + vma->node.size, + I915_GTT_PAGE_SIZE_2M))) { + vaddr = kmap_atomic_px(pd); + vaddr[idx.pde] |= GEN8_PDE_IPS_64K; + kunmap_atomic(vaddr); + } + } + } while (iter->sg); } diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h index e9ec75b92f85..41df07e5e37a 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.h +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h @@ -149,6 +149,7 @@ typedef u64 gen8_ppgtt_pml4e_t; #define GEN8_PPAT_ELLC_OVERRIDE (0<<2) #define GEN8_PPAT(i, x) ((u64)(x) << ((i) * 8)) +#define GEN8_PDE_IPS_64K BIT(11) #define GEN8_PDE_PS_2M BIT(7) #define GEN8_PDPE_PS_1G BIT(7)