From patchwork Wed Jun 21 20:33:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 9802839 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 75F3C6038C for ; Wed, 21 Jun 2017 20:33:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6676828512 for ; Wed, 21 Jun 2017 20:33:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5B24028554; Wed, 21 Jun 2017 20:33:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0ED1428512 for ; Wed, 21 Jun 2017 20:33:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6B3756E582; Wed, 21 Jun 2017 20:33:56 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1B2A06E580 for ; Wed, 21 Jun 2017 20:33:54 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Jun 2017 13:33:53 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.39,370,1493708400"; d="scan'208";a="870413093" Received: from mutux-mobl.ger.corp.intel.com (HELO mwahaha.ger.corp.intel.com) ([10.252.23.195]) by FMSMGA003.fm.intel.com with ESMTP; 21 Jun 2017 13:33:52 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Wed, 21 Jun 2017 21:33:31 +0100 Message-Id: <20170621203345.26320-6-matthew.auld@intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170621203345.26320-1-matthew.auld@intel.com> References: <20170621203345.26320-1-matthew.auld@intel.com> Subject: [Intel-gfx] [PATCH 05/19] drm/i915: align the vma start to the largest gtt page size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP For the 48b PPGTT try to align the vma start address to the required page size boundary to guarantee we use said page size in the gtt. If we are dealing with multiple page sizes, we can't guarantee anything and just align to the largest. For soft pinning and objects which need to be tightly packed into the lower 32bits we don't force any alignment. v2: various improvements suggested by Chris Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson --- drivers/gpu/drm/i915/i915_vma.c | 15 +++++++++++++++ drivers/gpu/drm/i915/i915_vma.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 958be0a95960..cee1d00dc085 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -471,6 +471,9 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) if (ret) return ret; + vma->page_sizes.phys = obj->mm.page_sizes.phys; + vma->page_sizes.sg = obj->mm.page_sizes.sg; + if (flags & PIN_OFFSET_FIXED) { u64 offset = flags & PIN_OFFSET_MASK; if (!IS_ALIGNED(offset, alignment) || @@ -485,6 +488,18 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) if (ret) goto err_unpin; } else { + /* We only support huge gtt pages through the 48b PPGTT, + * however we also don't want to force any alignment for + * objects which need to be tightly packed into the low 32bits. + */ + if (end > (1ULL << 32) && + vma->page_sizes.sg > I915_GTT_PAGE_SIZE) { + u64 page_alignment = + rounddown_pow_of_two(vma->page_sizes.sg); + + alignment = max(alignment, page_alignment); + } + ret = i915_gem_gtt_insert(vma->vm, &vma->node, size, alignment, obj->cache_level, start, end, flags); diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index 4a673fc1a432..834f7ca2ada2 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -52,6 +52,7 @@ struct i915_vma { struct drm_i915_fence_reg *fence; struct reservation_object *resv; /** Alias of obj->resv */ struct sg_table *pages; + struct i915_page_sizes page_sizes; void __iomem *iomap; u64 size; u64 display_alignment;