Message ID | 20170622115555.12176-11-ville.syrjala@linux.intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Quoting ville.syrjala@linux.intel.com (2017-06-22 12:55:48) > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Bspec claims that HWSTAM is only 16 bits on gen3, but the other > interrupts registers are 32 bits and there are 18 valid interrupt > bits. Hence a 16 bit HWSTAM wouldn't be able to contain all the > bits, so it seems the spec is incorrect about the size of the > register. And indeed I can clear bits 16 and 17 just fine with > a 32 bit write. So let's adjust the code to treat the register > as 32 bits. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b4c9a6a7023a..2b8aeb79a7a8 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3793,7 +3793,7 @@ static void i915_irq_preinstall(struct drm_device * dev) i9xx_pipestat_irq_reset(dev_priv); - I915_WRITE16(HWSTAM, 0xeffe); + I915_WRITE(HWSTAM, 0xffffeffe); GEN3_IRQ_RESET(); } @@ -3989,7 +3989,7 @@ static void i915_irq_uninstall(struct drm_device * dev) i9xx_pipestat_irq_reset(dev_priv); - I915_WRITE16(HWSTAM, 0xffff); + I915_WRITE(HWSTAM, 0xffffffff); GEN3_IRQ_RESET(); }