From patchwork Mon Jun 26 15:48:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 9809967 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3357B60209 for ; Mon, 26 Jun 2017 15:48:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 34E70285FB for ; Mon, 26 Jun 2017 15:48:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 29B592861A; Mon, 26 Jun 2017 15:48:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 55E5E285FB for ; Mon, 26 Jun 2017 15:48:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9AD146E03C; Mon, 26 Jun 2017 15:48:25 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9245B6E03C for ; Mon, 26 Jun 2017 15:48:23 +0000 (UTC) Received: by mail-wm0-x242.google.com with SMTP id 131so971141wmq.2 for ; Mon, 26 Jun 2017 08:48:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ursulin-net.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UBNW/ECRavz1bVJZqYpWzxeROUUR5VXpzQb0sWTsJCo=; b=y0ET0GcWVecNW9Xj6QeZA4SQH9FJ69c2BIJuEPBYq585k60/4xNnd2HqLRfGhZVS5N RlP/hgvcn2fOUvGLCtkuyVA7HCt1vR84WMe1rYvCc1C+ioq9tEV7RcIz4O3S3GRzYLkb czR/llLMDDvc/bWqrwJo9r9JkjRtvZoXcnyI7NCHEf7wo9FgiQE3ePVbYWxc5pV3G/yf tLynLNvKC3MKUHvE1VjfDYtvYLzSKkw2rY+Ber1H6zq6aVrxdkUhsgVkbHcgLFyXQ7Cd 5l8s9ZyJcf4+FcddHuFYx1D2/1yh2Ybq3ix9h6muAdKLa+OzqZ3+RSEK6wY8nH57kjh/ yzaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UBNW/ECRavz1bVJZqYpWzxeROUUR5VXpzQb0sWTsJCo=; b=Xq4dg71VpB+Q44OY4yV7Tyx/QpAezvuARx+AxC4kRLS7cqE2b2Y3PQTfCMZd84dF00 jzL0CsAH8T9f+6aLvZgYdnio5pDHNX6RzpLK+IxKg0rGWz55Jf5goloWILqPD9hGpll2 sl6NEceULFLpl7i0Vsynr0MIXdLbUQImLwWjeakHkTZAVCpxMgiZuTCpNRVKl/4Swpqh mIHq6Ysfik8Kh/STOaMzLJvPnA9d3gyiEzBuzEuyoPhnSiOYdyWZJr1xJqecj4hrrYS1 1WKl9m6hFXnTlAk7DtyMvScAOMEopl1lNU00NRa8WM0m/bq/HrA6FKEPlbFoKH7R2wp1 rDhw== X-Gm-Message-State: AKS2vOwzh5Yh3BeTZ5c64VCg6+/hkBRwtffjNKW1ZRnuHp2W8p5LRgNE ogcxWv0PJ6Yr+58unUA= X-Received: by 10.28.234.70 with SMTP id i67mr115598wmh.91.1498492101885; Mon, 26 Jun 2017 08:48:21 -0700 (PDT) Received: from t460p.intel ([95.146.144.225]) by smtp.gmail.com with ESMTPSA id p140sm526405wmb.28.2017.06.26.08.48.21 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 26 Jun 2017 08:48:21 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Mon, 26 Jun 2017 16:48:14 +0100 Message-Id: <20170626154814.31306-1-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.9.4 In-Reply-To: <20170518145826.29150-1-tvrtko.ursulin@linux.intel.com> References: <20170518145826.29150-1-tvrtko.ursulin@linux.intel.com> Cc: Ben Widawsky , Daniel Vetter Subject: [Intel-gfx] [RFC v6 2/2] drm/i915: Select engines via class and instance in execbuffer2 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Building on top of the previous patch which exported the concept of engine classes and instances, we can also use this instead of the current awkward engine selection uAPI. This is primarily interesting for the VCS engine selection which is a) currently done via disjoint set of flags, and b) the current I915_EXEC_BSD flags has different semantics depending on the underlying hardware which is bad. Proposed idea here is to reserve 8-bits of flags, to pass in the engine instance, re-use the existing engine selection bits for the class selection, and a new flag named I915_EXEC_CLASS_INSTANCE to tell the kernel this new engine selection API is in use. The new uAPI also removes access to the weak VCS engine balancing as currently existing in the driver. Example usage to send a command to VCS0: eb.flags = i915_execbuffer2_engine(I915_ENGINE_CLASS_VIDEO_DECODE, 0); Or to send a command to VCS1: eb.flags = i915_execbuffer2_engine(I915_ENGINE_CLASS_VIDEO_DECODE, 1); v2: * Fix unknown flags mask. * Use I915_EXEC_RING_MASK for class. (Chris Wilson) v3: * Add a map for fast class-instance engine lookup. (Chris Wilson) v4: * Update commit to reflect v3. * Export intel_engine_lookup for other users. (Chris Wilson) * Split out some warns. (Chris Wilson) v5: * Fixed shift and mask logic. * Rebased to be standalone. v6: * Rebased back to follow engine info ioctl. * Rename helper to intel_engine_lookup_user. (Chris Wilson) Signed-off-by: Tvrtko Ursulin Cc: Ben Widawsky Cc: Chris Wilson Cc: Daniel Vetter Cc: Joonas Lahtinen Cc: Jon Bloomfield Cc: "Rogozhkin, Dmitry V" Cc: Oscar Mateo Cc: "Gong, Zhipeng" --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem_execbuffer.c | 14 ++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_engine_cs.c | 28 ++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_ringbuffer.h | 3 +++ include/uapi/drm/i915_drm.h | 13 ++++++++++++- 6 files changed, 61 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 496565e1753f..4950de8c3de5 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2137,6 +2137,7 @@ struct drm_i915_private { struct pci_dev *bridge_dev; struct i915_gem_context *kernel_context; struct intel_engine_cs *engine[I915_NUM_ENGINES]; + struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1][MAX_ENGINE_INSTANCE + 1]; struct i915_vma *semaphore; struct drm_dma_handle *status_page_dmah; diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c index ec33b358fba9..63241840f00a 100644 --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c @@ -2050,6 +2050,17 @@ gen8_dispatch_bsd_engine(struct drm_i915_private *dev_priv, return file_priv->bsd_engine; } +static struct intel_engine_cs * +eb_select_engine_class_instance(struct drm_i915_private *i915, + struct drm_i915_gem_execbuffer2 *args) +{ + u8 class = args->flags & I915_EXEC_RING_MASK; + u8 instance = (args->flags & I915_EXEC_INSTANCE_MASK) >> + I915_EXEC_INSTANCE_SHIFT; + + return intel_engine_lookup_user(i915, class, instance); +} + #define I915_USER_RINGS (4) static const enum intel_engine_id user_ring_map[I915_USER_RINGS + 1] = { @@ -2068,6 +2079,9 @@ eb_select_engine(struct drm_i915_private *dev_priv, unsigned int user_ring_id = args->flags & I915_EXEC_RING_MASK; struct intel_engine_cs *engine; + if (args->flags & I915_EXEC_CLASS_INSTANCE) + return eb_select_engine_class_instance(dev_priv, args); + if (user_ring_id > I915_USER_RINGS) { DRM_DEBUG("execbuf with unknown ring: %u\n", user_ring_id); return NULL; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index c8647cfa81ba..834673c9ee6b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -95,6 +95,9 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) #define VIDEO_ENHANCEMENT_CLASS 2 #define COPY_ENGINE_CLASS 3 #define OTHER_CLASS 4 +#define MAX_ENGINE_CLASS 4 + +#define MAX_ENGINE_INSTANCE 1 /* PCI config space */ diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index a98669f6ad85..1089b22d2090 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -198,6 +198,15 @@ intel_engine_setup(struct drm_i915_private *dev_priv, GEM_BUG_ON(info->class >= ARRAY_SIZE(intel_engine_classes)); class_info = &intel_engine_classes[info->class]; + if (GEM_WARN_ON(info->class > MAX_ENGINE_CLASS)) + return -EINVAL; + + if (GEM_WARN_ON(info->instance > MAX_ENGINE_INSTANCE)) + return -EINVAL; + + if (GEM_WARN_ON(dev_priv->engine_class[info->class][info->instance])) + return -EINVAL; + GEM_BUG_ON(dev_priv->engine[id]); engine = kzalloc(sizeof(*engine), GFP_KERNEL); if (!engine) @@ -225,7 +234,9 @@ intel_engine_setup(struct drm_i915_private *dev_priv, ATOMIC_INIT_NOTIFIER_HEAD(&engine->context_status_notifier); + dev_priv->engine_class[info->class][info->instance] = engine; dev_priv->engine[id] = engine; + return 0; } @@ -1396,6 +1407,23 @@ int i915_gem_engine_info_ioctl(struct drm_device *dev, void *data, return 0; } +struct intel_engine_cs * +intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance) +{ + if (class >= ARRAY_SIZE(user_class_map)) + return NULL; + + class = user_class_map[class]; + + if (WARN_ON_ONCE(class > MAX_ENGINE_CLASS)) + return NULL; + + if (instance > MAX_ENGINE_INSTANCE) + return NULL; + + return i915->engine_class[class][instance]; +} + #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) #include "selftests/mock_engine.c" #endif diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index d33c93444c0d..283444f9be10 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -735,4 +735,7 @@ bool intel_engines_are_idle(struct drm_i915_private *dev_priv); void intel_engines_mark_idle(struct drm_i915_private *i915); void intel_engines_reset_default_submission(struct drm_i915_private *i915); +struct intel_engine_cs * +intel_engine_lookup_user(struct drm_i915_private *i915, u8 class, u8 instance); + #endif /* _INTEL_RINGBUFFER_H_ */ diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index fbb1f6b99959..c3fabb89e1c2 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -929,7 +929,13 @@ struct drm_i915_gem_execbuffer2 { * element). */ #define I915_EXEC_BATCH_FIRST (1<<18) -#define __I915_EXEC_UNKNOWN_FLAGS (-(I915_EXEC_BATCH_FIRST<<1)) + +#define I915_EXEC_CLASS_INSTANCE (1<<19) + +#define I915_EXEC_INSTANCE_SHIFT (20) +#define I915_EXEC_INSTANCE_MASK (0xff << I915_EXEC_INSTANCE_SHIFT) + +#define __I915_EXEC_UNKNOWN_FLAGS (-((1 << 27) << 1)) #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) #define i915_execbuffer2_set_context_id(eb2, context) \ @@ -937,6 +943,11 @@ struct drm_i915_gem_execbuffer2 { #define i915_execbuffer2_get_context_id(eb2) \ ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) +#define i915_execbuffer2_engine(class, instance) \ + (I915_EXEC_CLASS_INSTANCE | \ + (class) | \ + ((instance) << I915_EXEC_INSTANCE_SHIFT)) + struct drm_i915_gem_pin { /** Handle of the buffer to be pinned. */ __u32 handle;