From patchwork Mon Jul 10 13:02:11 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ville Syrjala X-Patchwork-Id: 9832931 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D63A160363 for ; Mon, 10 Jul 2017 13:02:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C7314283DA for ; Mon, 10 Jul 2017 13:02:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BBBD228470; Mon, 10 Jul 2017 13:02:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4989E28462 for ; Mon, 10 Jul 2017 13:02:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 052496E13A; Mon, 10 Jul 2017 13:02:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 38CE06E13A for ; Mon, 10 Jul 2017 13:02:19 +0000 (UTC) Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 10 Jul 2017 06:02:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.40,340,1496127600"; d="scan'208"; a="1170698656" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by fmsmga001.fm.intel.com with SMTP; 10 Jul 2017 06:02:11 -0700 Received: by stinkbox (sSMTP sendmail emulation); Mon, 10 Jul 2017 16:02:11 +0300 From: ville.syrjala@linux.intel.com To: intel-gfx@lists.freedesktop.org Date: Mon, 10 Jul 2017 16:02:11 +0300 Message-Id: <20170710130211.16859-1-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170707102450.3152-1-ville.syrjala@linux.intel.com> References: <20170707102450.3152-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Cc: Dhinakaran Pandiyan , Paulo Zanoni , Rodrigo Vivi Subject: [Intel-gfx] [PATCH v2 1/3] drm/i915: Fix up CNL cdclk related limits X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Ville Syrjälä Follow the GLK path when computing cdclk and related limits. CNL pipes also produce two pixels per clock, so that's what we should really use. However for the purposes of pixel rate calculations we will assume one pixel per clock to keep the voltage higher, at least until the missing voltage scaling for DDI clocks is implemented. For the HBR2 vs. audio issue the limit should more correctly be 336 MHz, but the GLK limit of 316.8 MHz works just as well and results in picking at least 336 MHz. Also toss in some related w/a numbers. v2: Assume 1 pixel per clock for the purposes of max pixel rate calculation until DDI clock voltage scaling is handled Cc: Paulo Zanoni Cc: Rodrigo Vivi Cc: Dhinakaran Pandiyan Cc: Maarten Lankhorst Signed-off-by: Ville Syrjälä Reviewed-by: Rodrigo Vivi Tested-by: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_cdclk.c | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 1241e5891b29..4b8eb6a7d852 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -1752,12 +1752,13 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, crtc_state->has_audio && crtc_state->port_clock >= 540000 && crtc_state->lane_count == 4) { - if (IS_CANNONLAKE(dev_priv)) - pixel_rate = max(316800, pixel_rate); - else if (IS_GEMINILAKE(dev_priv)) + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) { + /* Display WA #1145: glk,cnl */ pixel_rate = max(2 * 316800, pixel_rate); - else + } else if (IS_GEN9(dev_priv) || IS_BROADWELL(dev_priv)) { + /* Display WA #1144: skl,bxt */ pixel_rate = max(432000, pixel_rate); + } } /* According to BSpec, "The CD clock frequency must be at least twice @@ -1766,7 +1767,7 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state, * two pixels per clock. */ if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) { - if (IS_GEMINILAKE(dev_priv)) + if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) pixel_rate = max(2 * 2 * 96000, pixel_rate); else pixel_rate = max(2 * 96000, pixel_rate); @@ -1999,7 +2000,14 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) { int max_cdclk_freq = dev_priv->max_cdclk_freq; - if (IS_GEMINILAKE(dev_priv)) + if (INTEL_GEN(dev_priv) >= 10) + /* + * FIXME: Allow '2 * max_cdclk_freq' + * once DDI clock voltage requirements are + * handled correctly. + */ + return max_cdclk_freq; + else if (IS_GEMINILAKE(dev_priv)) /* * FIXME: Limiting to 99% as a temporary workaround. See * glk_calc_cdclk() for details.