| Message ID | 20170714151549.30065-2-lionel.g.landwerlin@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 14 July 2017 at 16:15, Lionel Landwerlin <lionel.g.landwerlin@intel.com> wrote: > We were reserving fewer dwords in the ring than necessary. Indeed > we're always writing all registers once, so discard the actual number > of registers given by the user and just program the whitelisted ones > once. > > Reported-by: Matthew Auld <matthew.william.auld@gmail.com> Fixes: 19f81df2859e ("drm/i915/perf: Add OA unit support for Gen 8+") > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > Cc: <stable@vger.kernel.org> # v4.12+ Reviewed-by: Matthew Auld <matthew.auld@intel.com>
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index d9f77a4d85db..ed396f7b7dca 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1601,11 +1601,11 @@ static int gen8_emit_oa_config(struct drm_i915_gem_request *req) u32 *cs; int i; - cs = intel_ring_begin(req, n_flex_regs * 2 + 4); + cs = intel_ring_begin(req, ARRAY_SIZE(flex_mmio) * 2 + 4); if (IS_ERR(cs)) return PTR_ERR(cs); - *cs++ = MI_LOAD_REGISTER_IMM(n_flex_regs + 1); + *cs++ = MI_LOAD_REGISTER_IMM(ARRAY_SIZE(flex_mmio) + 1); *cs++ = i915_mmio_reg_offset(GEN8_OACTXCONTROL); *cs++ = (dev_priv->perf.oa.period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
We were reserving fewer dwords in the ring than necessary. Indeed we're always writing all registers once, so discard the actual number of registers given by the user and just program the whitelisted ones once. Reported-by: Matthew Auld <matthew.william.auld@gmail.com> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: <stable@vger.kernel.org> # v4.12+ --- drivers/gpu/drm/i915/i915_perf.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)