From patchwork Sat Jul 15 11:40:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Vetter X-Patchwork-Id: 9842325 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0B61A60212 for ; Sat, 15 Jul 2017 11:40:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EEE1B286FB for ; Sat, 15 Jul 2017 11:40:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E39BD2872B; Sat, 15 Jul 2017 11:40:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8AC0B286FB for ; Sat, 15 Jul 2017 11:40:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AC6CF6E1C7; Sat, 15 Jul 2017 11:40:25 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4C77C6E14F for ; Sat, 15 Jul 2017 11:40:22 +0000 (UTC) Received: by mail-wm0-x243.google.com with SMTP id j85so14950303wmj.0 for ; Sat, 15 Jul 2017 04:40:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ffwll.ch; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Xl7lTLgEtoAiac4/qy9ATS4AgElS4mhXGrmqHmlrRNk=; b=UbktN60OC/ovldOIPM44SAhL5uXBDduyh70phpzITRrXRSfHNyZpK39LyhCs3F2qls a3RN3eXA7QBvhEctIrFxltWagi2Ta+Hh+jBRRXQdtJzkkCWJuV9/IYF4OMGIc5IAS3Pq WleSXvu6nOTyixWeNIpJczC1vhcYQjCzI7qnU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Xl7lTLgEtoAiac4/qy9ATS4AgElS4mhXGrmqHmlrRNk=; b=GYomyF/yQydXYLudYtpezOTZItStJWmDGCjdSne3FfpuwmAoQragyB0SGtZWkQpn81 JYLRB3IwX+KjnsjhxL9WZC6rnK2kMgk+P9pj6ydt9/h6AA0yLHhmQpfSpfjMsQj1mNiV o7zEHTp/Jez1Ar5CJ2sw8XN1izbv55GpyZ19eCp1AhX6F7UEWMJkO20dTiKYBpCURrjo WRhYIyv70A+SAXRkdjc4+xkaNmVMUmqQxmiaKPIDZt64AsxP4RT90dP6CT2TUOxQTA3I 0S4RDIX4Pdp/3DtV2DW1FadGkWd1JvhZSAvFgdmx2oLKqBki1nCYjxxgQRPUNH3o6Hiy /0Lg== X-Gm-Message-State: AIVw111R9V5Q/kW7CMEinIvgR6PwPIqFBqKzoTFO2950A96M/MdHY6oe paXMqzpyiKZ2HzGBpTI= X-Received: by 10.80.208.194 with SMTP id g2mr10460564edf.92.1500118820618; Sat, 15 Jul 2017 04:40:20 -0700 (PDT) Received: from phenom.ffwll.local ([2a02:168:5640:0:960b:2678:e223:c1c6]) by smtp.gmail.com with ESMTPSA id c8sm5898449edc.13.2017.07.15.04.40.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 15 Jul 2017 04:40:18 -0700 (PDT) From: Daniel Vetter To: Intel Graphics Development Date: Sat, 15 Jul 2017 13:40:01 +0200 Message-Id: <20170715114006.6380-3-daniel.vetter@ffwll.ch> X-Mailer: git-send-email 2.13.2 In-Reply-To: <20170715114006.6380-1-daniel.vetter@ffwll.ch> References: <20170715114006.6380-1-daniel.vetter@ffwll.ch> MIME-Version: 1.0 Cc: Daniel Vetter , Daniel Vetter Subject: [Intel-gfx] [PATCH 2/7] drm/i915: Unbreak gpu reset vs. modeset locking X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Taking the modeset locks unconditionally isn't the greatest idea, because atm that part is still broken and times out (and then atomic keels over). And there's really no reason to do so, the old code didn't do that either. To make the patch a bit simpler let's also nuke 2 cases that are only around for the old mmioflip paths. Atomic nonblocking workers will not die (minus bugs) when a gpu reset happens. And of course this doesn't fix any of the gpu reset vs. modeset deadlock fun, but it at least stop modern CI machines from keeling over all over the place for no reason at all. And we still have the explicit testcases to run the fake gpu reset, so coverage isn't that much worse. v2: Split out additional changes on top, restrict this to purely reducing the critical section of modeset locks. Fixes: 739748939974 ("drm/i915: Fix modeset handling during gpu reset, v5.") Cc: Maarten Lankhorst Cc: Ville Syrjälä Signed-off-by: Daniel Vetter Reviewed-by: Maarten Lankhorst --- drivers/gpu/drm/i915/intel_display.c | 53 +++++++++--------------------------- 1 file changed, 13 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index f69333b8995c..e3c55a996f6b 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -3413,26 +3413,6 @@ static void intel_complete_page_flips(struct drm_i915_private *dev_priv) intel_finish_page_flip_cs(dev_priv, crtc->pipe); } -static void intel_update_primary_planes(struct drm_device *dev) -{ - struct drm_crtc *crtc; - - for_each_crtc(dev, crtc) { - struct intel_plane *plane = to_intel_plane(crtc->primary); - struct intel_plane_state *plane_state = - to_intel_plane_state(plane->base.state); - - if (plane_state->base.visible) { - trace_intel_update_plane(&plane->base, - to_intel_crtc(crtc)); - - plane->update_plane(plane, - to_intel_crtc_state(crtc->state), - plane_state); - } - } -} - static int __intel_display_resume(struct drm_device *dev, struct drm_atomic_state *state, @@ -3485,6 +3465,12 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv) struct drm_atomic_state *state; int ret; + + /* reset doesn't touch the display, but flips might get nuked anyway, */ + if (!i915.force_reset_modeset_test && + !gpu_reset_clobbers_display(dev_priv)) + return; + /* * Need mode_config.mutex so that we don't * trample ongoing ->detect() and whatnot. @@ -3498,12 +3484,6 @@ void intel_prepare_reset(struct drm_i915_private *dev_priv) drm_modeset_backoff(ctx); } - - /* reset doesn't touch the display, but flips might get nuked anyway, */ - if (!i915.force_reset_modeset_test && - !gpu_reset_clobbers_display(dev_priv)) - return; - /* * Disabling the crtcs gracefully seems nicer. Also the * g33 docs say we should at least disable all the planes. @@ -3533,6 +3513,11 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) struct drm_atomic_state *state = dev_priv->modeset_restore_state; int ret; + /* reset doesn't touch the display, but flips might get nuked anyway, */ + if (!i915.force_reset_modeset_test && + !gpu_reset_clobbers_display(dev_priv)) + return; + /* * Flips in the rings will be nuked by the reset, * so complete all pending flips so that user space @@ -3544,22 +3529,10 @@ void intel_finish_reset(struct drm_i915_private *dev_priv) /* reset doesn't touch the display */ if (!gpu_reset_clobbers_display(dev_priv)) { - if (!state) { - /* - * Flips in the rings have been nuked by the reset, - * so update the base address of all primary - * planes to the the last fb to make sure we're - * showing the correct fb after a reset. - * - * FIXME: Atomic will make this obsolete since we won't schedule - * CS-based flips (which might get lost in gpu resets) any more. - */ - intel_update_primary_planes(dev); - } else { - ret = __intel_display_resume(dev, state, ctx); + /* for testing only restore the display */ + ret = __intel_display_resume(dev, state, ctx); if (ret) DRM_ERROR("Restoring old state failed with %i\n", ret); - } } else { /* * The display has been reset as well,