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[18/21] drm/i915: disable platform support for vGPU huge gtt pages

Message ID 20170725192133.2012-19-matthew.auld@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Matthew Auld July 25, 2017, 7:21 p.m. UTC 
Currently gvt gtt handling doesn't support huge page entries, so disable
for now.

Suggested-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 9 +++++++++
 1 file changed, 9 insertions(+)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 74ad006cac15..c171511d3251 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4871,6 +4871,15 @@  int i915_gem_init(struct drm_i915_private *dev_priv)
 
 	mutex_lock(&dev_priv->drm.struct_mutex);
 
+	/* If the guest supports the 48b PPGGT, then we need to fallback to 4K
+	 * pages, since gvt gtt handling doesn't support huge page entries - we
+	 * need to check either hypervisor mm can support huge guest page or
+	 * just do emulation in gvt.
+	 */
+	if (USES_FULL_48BIT_PPGTT(dev_priv) && intel_vgpu_active(dev_priv))
+		mkwrite_device_info(dev_priv)->page_size_mask =
+			I915_GTT_PAGE_SIZE_4K;
+
 	dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1);
 
 	if (!i915.enable_execlists) {