From patchwork Tue Aug 1 22:47:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Ben Widawsky X-Patchwork-Id: 9875649 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5E1D06038F for ; Tue, 1 Aug 2017 22:48:05 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4F576286F4 for ; Tue, 1 Aug 2017 22:48:05 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 43F6328749; Tue, 1 Aug 2017 22:48:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9DAB8286F4 for ; Tue, 1 Aug 2017 22:48:02 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5125A6EEE7; Tue, 1 Aug 2017 22:48:01 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail.bwidawsk.net (zangief.bwidawsk.net [107.170.211.233]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1B60E6EEE6; Tue, 1 Aug 2017 22:47:59 +0000 (UTC) Received: by mail.bwidawsk.net (Postfix, from userid 5001) id 4DCC71200DF; Tue, 1 Aug 2017 15:47:59 -0700 (PDT) Received: from mail.bwidawsk.net (c-73-37-61-163.hsd1.or.comcast.net [73.37.61.163]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mail.bwidawsk.net (Postfix) with ESMTPSA id 95D8112000A; Tue, 1 Aug 2017 15:47:54 -0700 (PDT) Date: Tue, 1 Aug 2017 15:47:53 -0700 From: Ben Widawsky To: Kenneth Graunke Message-ID: <20170801224753.GA2441@mail.bwidawsk.net> References: <20170801165817.7063-1-ben@bwidawsk.net> <20170801165817.7063-6-ben@bwidawsk.net> <1530601.zh7oHHzDPt@kirito> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1530601.zh7oHHzDPt@kirito> User-Agent: Mutt/1.8.3 (2017-05-23) Cc: intel-gfx@lists.freedesktop.org, Daniel Stone , DRI Development Subject: Re: [Intel-gfx] [PATCH 6/6] [v4] drm/i915: Add support for CCS modifiers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP On 17-08-01 15:43:50, Kenneth Graunke wrote: >On Tuesday, August 1, 2017 9:58:17 AM PDT Ben Widawsky wrote: >> v2: >> - Support sprite plane. >> - Support pipe C/D limitation on GEN9. >> >> v3: >> - Rename structure (Ville) >> - Handle GLK (Ville) >> >> v4: >> - Fix PIPE_C check, introduced in v2 (Daniel) >> - Whitespace fix (Daniel) >> >> Cc: Daniel Stone >> Cc: Kristian Høgsberg >> Signed-off-by: Ben Widawsky >> --- >> drivers/gpu/drm/i915/intel_display.c | 30 +++++++++++++++++++++++++++--- >> drivers/gpu/drm/i915/intel_sprite.c | 28 +++++++++++++++++++++++++++- >> 2 files changed, 54 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c >> index ad49b99ef25f..0dc9f40edc7e 100644 >> --- a/drivers/gpu/drm/i915/intel_display.c >> +++ b/drivers/gpu/drm/i915/intel_display.c >> @@ -93,7 +93,17 @@ static const uint32_t skl_primary_formats[] = { >> DRM_FORMAT_VYUY, >> }; >> >> -static const uint64_t skl_format_modifiers[] = { >> +static const uint64_t skl_format_modifiers_noccs[] = { >> + I915_FORMAT_MOD_Yf_TILED, >> + I915_FORMAT_MOD_Y_TILED, >> + I915_FORMAT_MOD_X_TILED, >> + DRM_FORMAT_MOD_LINEAR, >> + DRM_FORMAT_MOD_INVALID >> +}; >> + >> +static const uint64_t skl_format_modifiers_ccs[] = { >> + I915_FORMAT_MOD_Yf_TILED_CCS, >> + I915_FORMAT_MOD_Y_TILED_CCS, >> I915_FORMAT_MOD_Yf_TILED, >> I915_FORMAT_MOD_Y_TILED, >> I915_FORMAT_MOD_X_TILED, >> @@ -13853,6 +13863,10 @@ static bool skl_mod_supported(uint32_t format, uint64_t modifier) >> case DRM_FORMAT_XBGR8888: >> case DRM_FORMAT_ARGB8888: >> case DRM_FORMAT_ABGR8888: >> + if (modifier == I915_FORMAT_MOD_Yf_TILED_CCS || >> + modifier == I915_FORMAT_MOD_Y_TILED_CCS) >> + return true; >> + /* fall through */ >> case DRM_FORMAT_RGB565: >> case DRM_FORMAT_XRGB2101010: >> case DRM_FORMAT_XBGR2101010: >> @@ -14099,10 +14113,20 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe) >> primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe); >> primary->check_plane = intel_check_primary_plane; >> >> - if (INTEL_GEN(dev_priv) >= 9) { >> + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { >> + intel_primary_formats = skl_primary_formats; >> + num_formats = ARRAY_SIZE(skl_primary_formats); >> + modifiers = skl_format_modifiers_ccs; >> + >> + primary->update_plane = skylake_update_primary_plane; >> + primary->disable_plane = skylake_disable_primary_plane; >> + } else if (INTEL_GEN(dev_priv) >= 9) { >> intel_primary_formats = skl_primary_formats; >> num_formats = ARRAY_SIZE(skl_primary_formats); >> - modifiers = skl_format_modifiers; >> + if (pipe < PIPE_C) >> + modifiers = skl_format_modifiers_ccs; >> + else >> + modifiers = skl_format_modifiers_noccs; >> >> primary->update_plane = skylake_update_primary_plane; >> primary->disable_plane = skylake_disable_primary_plane; >> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c >> index b1cc4835b963..5a2b3f3693a6 100644 >> --- a/drivers/gpu/drm/i915/intel_sprite.c >> +++ b/drivers/gpu/drm/i915/intel_sprite.c >> @@ -1085,7 +1085,17 @@ static uint32_t skl_plane_formats[] = { >> DRM_FORMAT_VYUY, >> }; >> >> +static const uint64_t skl_plane_format_modifiers_noccs[] = { >> + I915_FORMAT_MOD_Yf_TILED, >> + I915_FORMAT_MOD_Y_TILED, >> + I915_FORMAT_MOD_X_TILED, >> + DRM_FORMAT_MOD_LINEAR, >> + DRM_FORMAT_MOD_INVALID >> +}; >> + >> static const uint64_t skl_plane_format_modifiers[] = { >> + I915_FORMAT_MOD_Yf_TILED_CCS, >> + I915_FORMAT_MOD_Y_TILED_CCS, >> I915_FORMAT_MOD_Yf_TILED, >> I915_FORMAT_MOD_Y_TILED, >> I915_FORMAT_MOD_X_TILED, >> @@ -1148,6 +1158,9 @@ static bool skl_sprite_plane_format_mod_supported(struct drm_plane *plane, >> case DRM_FORMAT_XBGR8888: >> case DRM_FORMAT_ARGB8888: >> case DRM_FORMAT_ABGR8888: >> + if (modifier == I915_FORMAT_MOD_Y_TILED_CCS || >> + modifier == I915_FORMAT_MOD_Yf_TILED_CCS) >> + return true; >> case DRM_FORMAT_RGB565: >> case DRM_FORMAT_XRGB2101010: >> case DRM_FORMAT_XBGR2101010: >> @@ -1230,7 +1243,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, >> } >> intel_plane->base.state = &state->base; >> >> - if (INTEL_GEN(dev_priv) >= 9) { >> + if (INTEL_GEN(dev_priv) >= 10) { > >I think this should be INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv). > >With that fixed, this patch would be: >Reviewed-by: Kenneth Graunke > >for what it's worth (I'm not that familiar with display). > Thanks. Here is what I've changed locally which didn't match the primary support: >> intel_plane->can_scale = true; >> state->scaler_id = -1; >> >> @@ -1240,6 +1253,19 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, >> plane_formats = skl_plane_formats; >> num_plane_formats = ARRAY_SIZE(skl_plane_formats); >> modifiers = skl_plane_format_modifiers; >> + } else if (INTEL_GEN(dev_priv) >= 9) { >> + intel_plane->can_scale = true; >> + state->scaler_id = -1; >> + >> + intel_plane->update_plane = skl_update_plane; >> + intel_plane->disable_plane = skl_disable_plane; >> + >> + plane_formats = skl_plane_formats; >> + num_plane_formats = ARRAY_SIZE(skl_plane_formats); >> + if (pipe >= PIPE_C) >> + modifiers = skl_plane_format_modifiers_noccs; >> + else >> + modifiers = skl_plane_format_modifiers; >> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { >> intel_plane->can_scale = false; >> intel_plane->max_downscale = 1; Reviewed-by: Kenneth Graunke diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c index 5a2b3f3693a6..1c484195fd0f 100644 --- a/drivers/gpu/drm/i915/intel_sprite.c +++ b/drivers/gpu/drm/i915/intel_sprite.c @@ -1093,7 +1093,7 @@ static const uint64_t skl_plane_format_modifiers_noccs[] = { DRM_FORMAT_MOD_INVALID }; -static const uint64_t skl_plane_format_modifiers[] = { +static const uint64_t skl_plane_format_modifiers_ccs[] = { I915_FORMAT_MOD_Yf_TILED_CCS, I915_FORMAT_MOD_Y_TILED_CCS, I915_FORMAT_MOD_Yf_TILED, @@ -1243,7 +1243,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, } intel_plane->base.state = &state->base; - if (INTEL_GEN(dev_priv) >= 10) { + if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) { intel_plane->can_scale = true; state->scaler_id = -1; @@ -1252,7 +1252,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane_formats = skl_plane_formats; num_plane_formats = ARRAY_SIZE(skl_plane_formats); - modifiers = skl_plane_format_modifiers; + modifiers = skl_plane_format_modifiers_ccs; } else if (INTEL_GEN(dev_priv) >= 9) { intel_plane->can_scale = true; state->scaler_id = -1; @@ -1262,10 +1262,10 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv, plane_formats = skl_plane_formats; num_plane_formats = ARRAY_SIZE(skl_plane_formats); - if (pipe >= PIPE_C) - modifiers = skl_plane_format_modifiers_noccs; + if (pipe < PIPE_C) + modifiers = skl_plane_format_modifiers_ccs; else - modifiers = skl_plane_format_modifiers; + modifiers = skl_plane_format_modifiers_noccs; } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { intel_plane->can_scale = false;