| Message ID | 20170809162441.10676-1-michal.wajdeczko@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 08/09/2017 09:24 AM, Michal Wajdeczko wrote: > We will need them in G2H communication to properly handle > responses and requests from the Guc. > > v2: keep irq enabled while disabling GuC logging (Oscar) > > Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> > Cc: Oscar Mateo <oscar.mateo@intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Michel Thierry <michel.thierry@intel.com> > --- > drivers/gpu/drm/i915/i915_guc_submission.c | 2 +- > drivers/gpu/drm/i915/intel_guc_log.c | 10 ++++++---- > drivers/gpu/drm/i915/intel_uc.c | 2 +- > 3 files changed, 8 insertions(+), 6 deletions(-) Acked-by: Oscar Mateo <oscar.mateo@intel.com> > diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c > index 48a1e93..509497e 100644 > --- a/drivers/gpu/drm/i915/i915_guc_submission.c > +++ b/drivers/gpu/drm/i915/i915_guc_submission.c > @@ -1328,7 +1328,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv) > if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) > return 0; > > - if (i915.guc_log_level >= 0) > + if (HAS_GUC_CT(dev_priv) || i915.guc_log_level >= 0) > gen9_enable_guc_interrupts(dev_priv); > > ctx = dev_priv->kernel_context; > diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c > index acd9a3f..64fb879 100644 > --- a/drivers/gpu/drm/i915/intel_guc_log.c > +++ b/drivers/gpu/drm/i915/intel_guc_log.c > @@ -505,8 +505,9 @@ static void guc_flush_logs(struct intel_guc *guc) > if (!i915.enable_guc_submission || (i915.guc_log_level < 0)) > return; > > - /* First disable the interrupts, will be renabled afterwards */ > - gen9_disable_guc_interrupts(dev_priv); > + /* GuC logging maybe the only user of Guc2Host interrupts */ > + if (!HAS_GUC_CT(dev_priv)) > + gen9_disable_guc_interrupts(dev_priv); > > /* Before initiating the forceful flush, wait for any pending/ongoing > * flush to complete otherwise forceful flush may not actually happen. > @@ -663,8 +664,9 @@ void i915_guc_log_unregister(struct drm_i915_private *dev_priv) > return; > > mutex_lock(&dev_priv->drm.struct_mutex); > - /* GuC logging is currently the only user of Guc2Host interrupts */ > - gen9_disable_guc_interrupts(dev_priv); > + /* GuC logging maybe the only user of Guc2Host interrupts */ > + if (!HAS_GUC_CT(dev_priv)) > + gen9_disable_guc_interrupts(dev_priv); > guc_log_runtime_destroy(&dev_priv->guc); > mutex_unlock(&dev_priv->drm.struct_mutex); > } > diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c > index 774d740..0209ad0 100644 > --- a/drivers/gpu/drm/i915/intel_uc.c > +++ b/drivers/gpu/drm/i915/intel_uc.c > @@ -395,7 +395,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) > > intel_guc_auth_huc(dev_priv); > if (i915.enable_guc_submission) { > - if (i915.guc_log_level >= 0) > + if (HAS_GUC_CT(dev_priv) || i915.guc_log_level >= 0) > gen9_enable_guc_interrupts(dev_priv); > > ret = i915_guc_submission_enable(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index 48a1e93..509497e 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -1328,7 +1328,7 @@ int intel_guc_resume(struct drm_i915_private *dev_priv) if (guc->fw.load_status != INTEL_UC_FIRMWARE_SUCCESS) return 0; - if (i915.guc_log_level >= 0) + if (HAS_GUC_CT(dev_priv) || i915.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); ctx = dev_priv->kernel_context; diff --git a/drivers/gpu/drm/i915/intel_guc_log.c b/drivers/gpu/drm/i915/intel_guc_log.c index acd9a3f..64fb879 100644 --- a/drivers/gpu/drm/i915/intel_guc_log.c +++ b/drivers/gpu/drm/i915/intel_guc_log.c @@ -505,8 +505,9 @@ static void guc_flush_logs(struct intel_guc *guc) if (!i915.enable_guc_submission || (i915.guc_log_level < 0)) return; - /* First disable the interrupts, will be renabled afterwards */ - gen9_disable_guc_interrupts(dev_priv); + /* GuC logging maybe the only user of Guc2Host interrupts */ + if (!HAS_GUC_CT(dev_priv)) + gen9_disable_guc_interrupts(dev_priv); /* Before initiating the forceful flush, wait for any pending/ongoing * flush to complete otherwise forceful flush may not actually happen. @@ -663,8 +664,9 @@ void i915_guc_log_unregister(struct drm_i915_private *dev_priv) return; mutex_lock(&dev_priv->drm.struct_mutex); - /* GuC logging is currently the only user of Guc2Host interrupts */ - gen9_disable_guc_interrupts(dev_priv); + /* GuC logging maybe the only user of Guc2Host interrupts */ + if (!HAS_GUC_CT(dev_priv)) + gen9_disable_guc_interrupts(dev_priv); guc_log_runtime_destroy(&dev_priv->guc); mutex_unlock(&dev_priv->drm.struct_mutex); } diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c index 774d740..0209ad0 100644 --- a/drivers/gpu/drm/i915/intel_uc.c +++ b/drivers/gpu/drm/i915/intel_uc.c @@ -395,7 +395,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv) intel_guc_auth_huc(dev_priv); if (i915.enable_guc_submission) { - if (i915.guc_log_level >= 0) + if (HAS_GUC_CT(dev_priv) || i915.guc_log_level >= 0) gen9_enable_guc_interrupts(dev_priv); ret = i915_guc_submission_enable(dev_priv);
We will need them in G2H communication to properly handle responses and requests from the Guc. v2: keep irq enabled while disabling GuC logging (Oscar) Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Oscar Mateo <oscar.mateo@intel.com> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Michel Thierry <michel.thierry@intel.com> --- drivers/gpu/drm/i915/i915_guc_submission.c | 2 +- drivers/gpu/drm/i915/intel_guc_log.c | 10 ++++++---- drivers/gpu/drm/i915/intel_uc.c | 2 +- 3 files changed, 8 insertions(+), 6 deletions(-)