| Message ID | 20170815181215.18310-10-matthew.auld@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Quoting Matthew Auld (2017-08-15 19:12:02) > + /* To support 64K PTE's we need to first enable the use of the > + * Intermediate-Page-Size(IPS) bit of the PDE field via some magical > + * mmio, otherwise the page-walker will simply ignore the IPS bit. This > + * shouldn't be needed after GEN10. > + */ > + if (HAS_PAGE_SIZE(dev_priv, I915_GTT_PAGE_SIZE_64K) && I presume we have some vague acknowledgement that snb+ can do 64k, so don't we need a IS_GEN(i915, 8, 10) here or is GEN8_GAM_ECO_DEV_RW_IA badly named? Or was snb just 32k like ilk? > + INTEL_GEN(dev_priv) <= 10) > + I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA, > + I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) | > + GAMW_ECO_ENABLE_64K_IPS_FIELD); > +
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1f69128a975c..f924a336aaa1 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4765,6 +4765,17 @@ int i915_gem_init_hw(struct drm_i915_private *dev_priv) } } + /* To support 64K PTE's we need to first enable the use of the + * Intermediate-Page-Size(IPS) bit of the PDE field via some magical + * mmio, otherwise the page-walker will simply ignore the IPS bit. This + * shouldn't be needed after GEN10. + */ + if (HAS_PAGE_SIZE(dev_priv, I915_GTT_PAGE_SIZE_64K) && + INTEL_GEN(dev_priv) <= 10) + I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA, + I915_READ(GEN8_GAMW_ECO_DEV_RW_IA) | + GAMW_ECO_ENABLE_64K_IPS_FIELD); + i915_gem_init_swizzling(dev_priv); /* diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b2d785969d17..995da42f797f 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2370,6 +2370,9 @@ enum i915_power_well_id { #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0) #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1<<18) +#define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080) +#define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF + #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1<<28)
Before we can enable 64K pages through the IPS bit, we must first enable it through MMIO, otherwise the page-walker will simply ignore it. Signed-off-by: Matthew Auld <matthew.auld@intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> --- drivers/gpu/drm/i915/i915_gem.c | 11 +++++++++++ drivers/gpu/drm/i915/i915_reg.h | 3 +++ 2 files changed, 14 insertions(+)