From patchwork Wed Aug 30 18:20:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lionel Landwerlin X-Patchwork-Id: 9930521 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2C2786022E for ; Wed, 30 Aug 2017 18:20:21 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 25F7D2874A for ; Wed, 30 Aug 2017 18:20:21 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1A9762874E; Wed, 30 Aug 2017 18:20:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D20052874A for ; Wed, 30 Aug 2017 18:20:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3218F6E4B9; Wed, 30 Aug 2017 18:20:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id DEA766E49B for ; Wed, 30 Aug 2017 18:20:16 +0000 (UTC) Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga104.jf.intel.com with ESMTP; 30 Aug 2017 11:20:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.41,449,1498546800"; d="scan'208";a="306244867" Received: from gkohane-mobl2.ger.corp.intel.com (HELO delly.ger.corp.intel.com) ([10.252.25.141]) by fmsmga004.fm.intel.com with ESMTP; 30 Aug 2017 11:20:15 -0700 From: Lionel Landwerlin To: intel-gfx@lists.freedesktop.org Date: Wed, 30 Aug 2017 19:20:04 +0100 Message-Id: <20170830182006.32644-3-lionel.g.landwerlin@intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170830182006.32644-1-lionel.g.landwerlin@intel.com> References: <20170830182006.32644-1-lionel.g.landwerlin@intel.com> Subject: [Intel-gfx] [RFC PATCH 2/4] drm/i915: extract per-ctx/indirect bb programming X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Let's put this in its own function to reuse it later. Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/intel_lrc.c | 33 +++++++++++++++++++-------------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 5b96b1e2353d..6da2b4f0c5a5 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1906,6 +1906,23 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) return indirect_ctx_offset; } +static void execlists_init_reg_state_wa_bb(u32 *regs, + struct intel_engine_cs *engine) +{ + struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; + u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); + + regs[CTX_RCS_INDIRECT_CTX + 1] = + (ggtt_offset + wa_ctx->indirect_ctx.offset) | + (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); + + regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] = + intel_lr_indirect_ctx_offset(engine) << 6; + + regs[CTX_BB_PER_CTX_PTR + 1] = + (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; +} + static void execlists_init_reg_state(u32 *regs, struct i915_gem_context *ctx, struct intel_engine_cs *engine, @@ -1948,20 +1965,8 @@ static void execlists_init_reg_state(u32 *regs, CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET, RING_INDIRECT_CTX_OFFSET(base), 0); - if (engine->wa_ctx.vma) { - struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; - u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); - - regs[CTX_RCS_INDIRECT_CTX + 1] = - (ggtt_offset + wa_ctx->indirect_ctx.offset) | - (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); - - regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] = - intel_lr_indirect_ctx_offset(engine) << 6; - - regs[CTX_BB_PER_CTX_PTR + 1] = - (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; - } + if (engine->wa_ctx.vma) + execlists_init_reg_state_wa_bb(regs, engine); } regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED;