From patchwork Fri Sep 1 17:12:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lionel Landwerlin X-Patchwork-Id: 9934911 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 453526016C for ; Fri, 1 Sep 2017 17:12:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2BC91223C6 for ; Fri, 1 Sep 2017 17:12:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 207E226E49; Fri, 1 Sep 2017 17:12:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B3705223C6 for ; Fri, 1 Sep 2017 17:12:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 0240F6E8A1; Fri, 1 Sep 2017 17:12:43 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5ED606E8A0 for ; Fri, 1 Sep 2017 17:12:41 +0000 (UTC) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga104.jf.intel.com with ESMTP; 01 Sep 2017 10:12:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.41,459,1498546800"; d="scan'208"; a="1213545336" Received: from delly.ld.intel.com ([10.103.239.215]) by fmsmga002.fm.intel.com with ESMTP; 01 Sep 2017 10:12:40 -0700 From: Lionel Landwerlin To: intel-gfx@lists.freedesktop.org Date: Fri, 1 Sep 2017 18:12:29 +0100 Message-Id: <20170901171230.28677-4-lionel.g.landwerlin@intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20170901171230.28677-1-lionel.g.landwerlin@intel.com> References: <20170901171230.28677-1-lionel.g.landwerlin@intel.com> Subject: [Intel-gfx] [RFC PATCH 3/4] drm/i915: Record the sseu configuration per-context & engine X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Chris Wilson We want to expose the ability to reconfigure the slices, subslice and eu per context and per engine. To facilitate that, store the current configuration on the context for each engine, which is initially set to the device default upon creation. v2: record sseu configuration per context & engine (Chris) Signed-off-by: Chris Wilson Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_drv.h | 19 ------------------- drivers/gpu/drm/i915/i915_gem_context.c | 6 ++++++ drivers/gpu/drm/i915/i915_gem_context.h | 21 +++++++++++++++++++++ drivers/gpu/drm/i915/intel_lrc.c | 23 +++++++++-------------- 4 files changed, 36 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4eea89751608..43d83ffae2d3 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -800,25 +800,6 @@ struct intel_csr { func(overlay_needs_physical); \ func(supports_tv); -struct sseu_dev_info { - u8 slice_mask; - u8 subslice_mask; - u8 eu_total; - u8 min_eu_per_subslice; - u8 max_eu_per_subslice; - u8 min_eu_in_pool; - /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ - u8 subslice_7eu[3]; - u8 has_slice_pg:1; - u8 has_subslice_pg:1; - u8 has_eu_pg:1; -}; - -static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) -{ - return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask); -} - /* Keep in gen based order, and chronological order within a gen */ enum intel_platform { INTEL_PLATFORM_UNINITIALIZED = 0, diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 58a2a44f88bd..97fcb01d70eb 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -257,6 +257,8 @@ __create_hw_context(struct drm_i915_private *dev_priv, struct drm_i915_file_private *file_priv) { struct i915_gem_context *ctx; + struct intel_engine_cs *engine; + enum intel_engine_id id; int ret; ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); @@ -305,6 +307,10 @@ __create_hw_context(struct drm_i915_private *dev_priv, * is no remap info, it will be a NOP. */ ctx->remap_slice = ALL_L3_SLICES(dev_priv); + /* On all engines, use the whole device by default */ + for_each_engine(engine, dev_priv, id) + ctx->engine[id].sseu = INTEL_INFO(dev_priv)->sseu; + i915_gem_context_set_bannable(ctx); ctx->ring_size = 4 * PAGE_SIZE; ctx->desc_template = diff --git a/drivers/gpu/drm/i915/i915_gem_context.h b/drivers/gpu/drm/i915/i915_gem_context.h index 44688e22a5c2..727b3b5bced1 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.h +++ b/drivers/gpu/drm/i915/i915_gem_context.h @@ -40,6 +40,25 @@ struct i915_hw_ppgtt; struct i915_vma; struct intel_ring; +struct sseu_dev_info { + u8 slice_mask; + u8 subslice_mask; + u8 eu_total; + u8 min_eu_per_subslice; + u8 max_eu_per_subslice; + u8 min_eu_in_pool; + /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ + u8 subslice_7eu[3]; + u8 has_slice_pg:1; + u8 has_subslice_pg:1; + u8 has_eu_pg:1; +}; + +static inline unsigned int sseu_subslice_total(const struct sseu_dev_info *sseu) +{ + return hweight8(sseu->slice_mask) * hweight8(sseu->subslice_mask); +} + #define DEFAULT_CONTEXT_HANDLE 0 /** @@ -158,6 +177,8 @@ struct i915_gem_context { u64 lrc_desc; int pin_count; bool initialised; + /** sseu: Control eu/slice partitioning */ + struct sseu_dev_info sseu; } engine[I915_NUM_ENGINES]; /** ring_size: size for allocating the per-engine ring buffer */ diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 8d1649899f12..1693fd9d279b 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1850,8 +1850,7 @@ int logical_xcs_ring_init(struct intel_engine_cs *engine) return logical_ring_init(engine); } -static u32 -make_rpcs(struct drm_i915_private *dev_priv) +static u32 make_rpcs(const struct sseu_dev_info *sseu) { u32 rpcs = 0; @@ -1861,25 +1860,21 @@ make_rpcs(struct drm_i915_private *dev_priv) * must make an explicit request through RPCS for full * enablement. */ - if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { + if (sseu->has_slice_pg) { rpcs |= GEN8_RPCS_S_CNT_ENABLE; - rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << - GEN8_RPCS_S_CNT_SHIFT; + rpcs |= hweight8(sseu->slice_mask) << GEN8_RPCS_S_CNT_SHIFT; rpcs |= GEN8_RPCS_ENABLE; } - if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { + if (sseu->has_subslice_pg) { rpcs |= GEN8_RPCS_SS_CNT_ENABLE; - rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) << - GEN8_RPCS_SS_CNT_SHIFT; + rpcs |= hweight8(sseu->subslice_mask) << GEN8_RPCS_SS_CNT_SHIFT; rpcs |= GEN8_RPCS_ENABLE; } - if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { - rpcs |= INTEL_INFO(dev_priv)->sseu.min_eu_per_subslice << - GEN8_RPCS_EU_MIN_SHIFT; - rpcs |= INTEL_INFO(dev_priv)->sseu.max_eu_per_subslice << - GEN8_RPCS_EU_MAX_SHIFT; + if (sseu->has_eu_pg) { + rpcs |= sseu->min_eu_per_subslice << GEN8_RPCS_EU_MIN_SHIFT; + rpcs |= sseu->max_eu_per_subslice << GEN8_RPCS_EU_MAX_SHIFT; rpcs |= GEN8_RPCS_ENABLE; } @@ -1993,7 +1988,7 @@ static void execlists_init_reg_state(u32 *regs, if (rcs) { regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, - make_rpcs(dev_priv)); + make_rpcs(&ctx->engine[engine->id].sseu)); i915_oa_init_reg_state(engine, ctx, regs); }