diff mbox

[7/8] drm/i915: Move execlist initialization into intel_engine_cs.c

Message ID 20170912083618.13009-8-mika.kuoppala@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Mika Kuoppala Sept. 12, 2017, 8:36 a.m. UTC
Move execlist init into a common engine setup. As it is
common to both guc and hw execlists.

Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c | 18 +++++++++++++++---
 drivers/gpu/drm/i915/intel_lrc.c       |  4 ----
 2 files changed, 15 insertions(+), 7 deletions(-)

Comments

Chris Wilson Sept. 12, 2017, 10:41 a.m. UTC | #1
Quoting Mika Kuoppala (2017-09-12 09:36:17)
> Move execlist init into a common engine setup. As it is
> common to both guc and hw execlists.

"Move execlist init into the commone engine setup for simplicity. At
present, it is split between the common setup and lrc for no real
reason. As we always inspect the execlists for debugging, we should
make sure that it is always initialised (and empty at start).

Plus now that we have a common substruct for execlists, having a common
initialiser makes our setup more self-descriptive."
 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

I would bump this to just after introduction of struct engine->execlist
-Chris
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index 0fb5a1f99349..4b9eaec50070 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -380,6 +380,20 @@  static void intel_engine_init_timeline(struct intel_engine_cs *engine)
 	engine->timeline = &engine->i915->gt.global_timeline.engine[engine->id];
 }
 
+static void intel_engine_init_execlist(struct intel_engine_cs *engine)
+{
+	struct intel_engine_execlist * const el = &engine->execlist;
+
+	el->port_mask = 1;
+	BUILD_BUG_ON_NOT_POWER_OF_2(el->port_mask + 1);
+	GEM_BUG_ON(el->port_mask >= EXECLIST_MAX_PORTS);
+
+	el->port_head = 0;
+
+	el->queue = RB_ROOT;
+	el->first = NULL;
+}
+
 /**
  * intel_engines_setup_common - setup engine state not requiring hw access
  * @engine: Engine to setup.
@@ -391,9 +405,7 @@  static void intel_engine_init_timeline(struct intel_engine_cs *engine)
  */
 void intel_engine_setup_common(struct intel_engine_cs *engine)
 {
-	engine->execlist.queue = RB_ROOT;
-	engine->execlist.first = NULL;
-
+	intel_engine_init_execlist(engine);
 	intel_engine_init_timeline(engine);
 	intel_engine_init_hangcheck(engine);
 	i915_gem_batch_pool_init(engine, &engine->batch_pool);
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0bc42a3f9528..1a1c68c53fbd 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1763,10 +1763,6 @@  logical_ring_setup(struct intel_engine_cs *engine)
 	/* Intentionally left blank. */
 	engine->buffer = NULL;
 
-	engine->execlist.port_mask = 1;
-	BUILD_BUG_ON_NOT_POWER_OF_2(engine->execlist.port_mask + 1);
-	GEM_BUG_ON(engine->execlist.port_mask >= EXECLIST_MAX_PORTS);
-
 	fw_domains = intel_uncore_forcewake_for_reg(dev_priv,
 						    RING_ELSP(engine),
 						    FW_REG_WRITE);