Message ID | 20170922151057.24782-4-lionel.g.landwerlin@intel.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 341a4205f480..699398257c37 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1894,13 +1894,6 @@ make_rpcs(struct drm_i915_private *dev_priv) { u32 rpcs = 0; - /* - * No explicit RPCS request is needed to ensure full - * slice/subslice/EU enablement prior to Gen9. - */ - if (INTEL_GEN(dev_priv) < 9) - return 0; - /* * Starting in Gen9, render power gating can leave * slice/subslice/EU in a partially enabled state. We