| Message ID | 20170922205343.16006-2-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Shouldn't we filter them out per platform? Anyways it is good for me Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> On Fri, Sep 22, 2017 at 08:53:42PM +0000, Paulo Zanoni wrote: > Looks like we were missing them. > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index 026fa54..64a4105 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -11336,6 +11336,18 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, > PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); > PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); > PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); > + PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); > + PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll0); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll1); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll2); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll3); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll6); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll8); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll9); > + PIPE_CONF_CHECK_X(dpll_hw_state.pll10); > + PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); > > PIPE_CONF_CHECK_X(dsi_pll.ctrl); > PIPE_CONF_CHECK_X(dsi_pll.div); > -- > 2.9.5 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Em Seg, 2017-09-25 às 16:16 -0700, Rodrigo Vivi escreveu: > Shouldn't we filter them out per platform? Yes, although doing it like this doesn't hurt much. See the cover letter: we can probably organize our structs in per-platform unions or something like that. Thanks for the review. > > Anyways it is good for me > > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > On Fri, Sep 22, 2017 at 08:53:42PM +0000, Paulo Zanoni wrote: > > Looks like we were missing them. > > > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > --- > > drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ > > 1 file changed, 12 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index 026fa54..64a4105 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -11336,6 +11336,18 @@ intel_pipe_config_compare(struct > > drm_i915_private *dev_priv, > > PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); > > PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); > > PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); > > + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); > > + PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); > > + PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll0); > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll1); > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll2); > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll3); > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll6); > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll8); > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll9); > > + PIPE_CONF_CHECK_X(dpll_hw_state.pll10); > > + PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); > > > > PIPE_CONF_CHECK_X(dsi_pll.ctrl); > > PIPE_CONF_CHECK_X(dsi_pll.div); > > -- > > 2.9.5 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 026fa54..64a4105 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -11336,6 +11336,18 @@ intel_pipe_config_compare(struct drm_i915_private *dev_priv, PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1); PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1); PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2); + PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); + PIPE_CONF_CHECK_X(dpll_hw_state.ebb0); + PIPE_CONF_CHECK_X(dpll_hw_state.ebb4); + PIPE_CONF_CHECK_X(dpll_hw_state.pll0); + PIPE_CONF_CHECK_X(dpll_hw_state.pll1); + PIPE_CONF_CHECK_X(dpll_hw_state.pll2); + PIPE_CONF_CHECK_X(dpll_hw_state.pll3); + PIPE_CONF_CHECK_X(dpll_hw_state.pll6); + PIPE_CONF_CHECK_X(dpll_hw_state.pll8); + PIPE_CONF_CHECK_X(dpll_hw_state.pll9); + PIPE_CONF_CHECK_X(dpll_hw_state.pll10); + PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12); PIPE_CONF_CHECK_X(dsi_pll.ctrl); PIPE_CONF_CHECK_X(dsi_pll.div);
Looks like we were missing them. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> --- drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)