From patchwork Fri Sep 29 16:10:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matthew Auld X-Patchwork-Id: 9978347 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 01E4E60329 for ; Fri, 29 Sep 2017 16:10:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E8C4B297C2 for ; Fri, 29 Sep 2017 16:10:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DDA2129845; Fri, 29 Sep 2017 16:10:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4D069297C2 for ; Fri, 29 Sep 2017 16:10:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CDDC66EBFF; Fri, 29 Sep 2017 16:10:49 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id B3DF16EBFF for ; Fri, 29 Sep 2017 16:10:48 +0000 (UTC) Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 29 Sep 2017 09:10:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos; i="5.42,453,1500966000"; d="scan'208"; a="1177056073" Received: from ialvarez-mobl.ger.corp.intel.com (HELO mwahaha.ger.corp.intel.com) ([10.252.10.71]) by orsmga001.jf.intel.com with ESMTP; 29 Sep 2017 09:10:47 -0700 From: Matthew Auld To: intel-gfx@lists.freedesktop.org Date: Fri, 29 Sep 2017 17:10:19 +0100 Message-Id: <20170929161032.24394-9-matthew.auld@intel.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170929161032.24394-1-matthew.auld@intel.com> References: <20170929161032.24394-1-matthew.auld@intel.com> Subject: [Intel-gfx] [PATCH 08/21] drm/i915: align the vma start to the largest gtt page size X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP For the 48b PPGTT try to align the vma start address to the required page size boundary to guarantee we use said page size in the gtt. If we are dealing with multiple page sizes, we can't guarantee anything and just align to the largest. For soft pinning and objects which need to be tightly packed into the lower 32bits we don't force any alignment. v2: various improvements suggested by Chris v3: use set_pages and better placement of page_sizes v4: prefer upper_32_bits() Signed-off-by: Matthew Auld Cc: Joonas Lahtinen Cc: Chris Wilson Reviewed-by: Chris Wilson Reviewed-by: Joonas Lahtinen --- drivers/gpu/drm/i915/i915_gem_gtt.c | 8 ++++++++ drivers/gpu/drm/i915/i915_vma.c | 13 +++++++++++++ drivers/gpu/drm/i915/i915_vma.h | 1 + 3 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c index c534b74eee32..c989e3d24e37 100644 --- a/drivers/gpu/drm/i915/i915_gem_gtt.c +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c @@ -226,6 +226,9 @@ static int ppgtt_set_pages(struct i915_vma *vma) vma->pages = vma->obj->mm.pages; + vma->page_sizes.phys = vma->obj->mm.page_sizes.phys; + vma->page_sizes.sg = vma->obj->mm.page_sizes.sg; + return 0; } @@ -238,6 +241,8 @@ static void clear_pages(struct i915_vma *vma) kfree(vma->pages); } vma->pages = NULL; + + memset(&vma->page_sizes, 0, sizeof(struct i915_page_sizes)); } static gen8_pte_t gen8_pte_encode(dma_addr_t addr, @@ -2538,6 +2543,9 @@ static int ggtt_set_pages(struct i915_vma *vma) if (ret) return ret; + vma->page_sizes.phys = vma->obj->mm.page_sizes.phys; + vma->page_sizes.sg = vma->obj->mm.page_sizes.sg; + return 0; } diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c index 49bf49571e47..5067eab27829 100644 --- a/drivers/gpu/drm/i915/i915_vma.c +++ b/drivers/gpu/drm/i915/i915_vma.c @@ -493,6 +493,19 @@ i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) if (ret) goto err_clear; } else { + /* + * We only support huge gtt pages through the 48b PPGTT, + * however we also don't want to force any alignment for + * objects which need to be tightly packed into the low 32bits. + */ + if (upper_32_bits(end) && + vma->page_sizes.sg > I915_GTT_PAGE_SIZE) { + u64 page_alignment = + rounddown_pow_of_two(vma->page_sizes.sg); + + alignment = max(alignment, page_alignment); + } + ret = i915_gem_gtt_insert(vma->vm, &vma->node, size, alignment, obj->cache_level, start, end, flags); diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h index e811067c7724..c59ba76613a3 100644 --- a/drivers/gpu/drm/i915/i915_vma.h +++ b/drivers/gpu/drm/i915/i915_vma.h @@ -55,6 +55,7 @@ struct i915_vma { void __iomem *iomap; u64 size; u64 display_alignment; + struct i915_page_sizes page_sizes; u32 fence_size; u32 fence_alignment;