From patchwork Tue Oct 3 07:06:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 9981811 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C903060365 for ; Tue, 3 Oct 2017 07:06:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BC4E128877 for ; Tue, 3 Oct 2017 07:06:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B14832887B; Tue, 3 Oct 2017 07:06:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 942BB28878 for ; Tue, 3 Oct 2017 07:06:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B8B7E6E3BE; Tue, 3 Oct 2017 07:06:24 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5D5066E3C2 for ; Tue, 3 Oct 2017 07:06:23 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Oct 2017 00:06:21 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,473,1500966000"; d="scan'208";a="906141462" Received: from mrsarkar-mobl2.amr.corp.intel.com (HELO rdvivi-vienna.intel.com) ([10.252.138.57]) by FMSMGA003.fm.intel.com with ESMTP; 03 Oct 2017 00:06:21 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Tue, 3 Oct 2017 00:06:03 -0700 Message-Id: <20171003070614.18396-3-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171003070614.18396-1-rodrigo.vivi@intel.com> References: <20171003070614.18396-1-rodrigo.vivi@intel.com> Cc: Rodrigo Vivi Subject: [Intel-gfx] [PATCH 02/13] drm/i915/cnl: Extract cnl_calc_pll_link following bxt style. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP No functional change. Just spliting the function for better port clock handling later. v2: Put link_clock *=2 inside the function only for DP, otherwise we mess up clocks on HDMI. (Caught by CI). Cc: Mika Kahola Signed-off-by: Rodrigo Vivi Reviewed-by: Mika Kahola --- drivers/gpu/drm/i915/intel_ddi.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index b5dd82a0e357..71040c3dd6fc 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1241,15 +1241,11 @@ static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) pipe_config->base.adjusted_mode.crtc_clock = dotclock; } -static void cnl_ddi_clock_get(struct intel_encoder *encoder, - struct intel_crtc_state *pipe_config) +static int cnl_calc_pll_link(struct drm_i915_private *dev_priv, + enum intel_dpll_id pll_id) { - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); int link_clock = 0; uint32_t cfgcr0; - enum intel_dpll_id pll_id; - - pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll); cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); @@ -1290,7 +1286,18 @@ static void cnl_ddi_clock_get(struct intel_encoder *encoder, link_clock *= 2; } - pipe_config->port_clock = link_clock; + return link_clock; +} + +static void cnl_ddi_clock_get(struct intel_encoder *encoder, + struct intel_crtc_state *pipe_config) +{ + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum intel_dpll_id pll_id; + + pll_id = intel_get_shared_dpll_id(dev_priv, pipe_config->shared_dpll); + + pipe_config->port_clock = cnl_calc_pll_link(dev_priv, pll_id); ddi_dotclock_get(pipe_config); }